
6-28
ColdFire CF4e Core User’s Manual
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Instruction Execution Times
6.5.5 Branch Instruction Execution Times
Table 6-13 shows general branch instruction timing.
Table 6-14 shows timing for Bcc instructions.
6.5.6 EMAC Instruction Execution Times
Table 6-15 specifies instruction execution times associated with the enhanced
multiply-accumulate (EMAC) execute engine.
unlk
Ax
1(1/0)
—
—
—
—
—
—
—
wddata.l
<ea>
—
1(1/0)
1(1/0)
1(1/0)
1(1/0)
2(1/0)
1(1/0)
—
wdebug.l
<ea>
—
3(2/0)
—
—
3(2/0)
—
—
—
1
n
is the number of registers moved by the MOVEM opcode.
PEA execution times are the same for (d16,PC).
PEA execution times are the same for (d8,PC,Xi*SF).
The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.
2
3
4
Table 6-13. General Branch Instruction Execution Times
Opcode
<ea>
Effective Address
Rn
(An)
(An)+
-(An)
(d16,An)
(d8,An,Xi*SF)
(xxx).wl
#<xxx>
bra
—
—
—
—
1(0/1)
1
1
Assumes branch acceleration. Depending on the pipeline status, execution times may vary from 1 to 3 cycles.
If predicted correctly by the hardware return stack.
If mispredicted by the hardware return stack.
If not predicted by the hardware return stack.
—
—
—
bsr
—
—
—
—
1(0/1)
1
—
—
—
jmp
<ea>
—
5(0/0)
—
—
5(0/0)
1
6(0/0)
1(0/0)
1
—
jsr
<ea>
—
5(0/1)
—
—
5(0/1)
6(0/1)
1(0/1)
1
—
rte
—
—
15(2/0)
—
—
—
—
—
rts
—
—
2(1/0)
2
9(1/0)
3
8(1/0)
4
2
3
4
—
—
—
—
—
Table 6-14. Bcc Instruction Execution Times
Opcode
Branch Cache
Correctly Predicts
Taken
Prediction Table
Correctly Predicts
Taken
Predicted
Correctly as
Not Taken
Predicted Incorrectly
bcc
0(0/0)
1(0/0)
1(0/0)
8(0/0)
Table 6-12. Miscellaneous Instruction Execution Times (Continued)
Opcode
<ea>
Effective Address
Rn
(An)
(An)+
-(An)
(d16,An)
(d8,An,Xi*SF)
(xxx).wl
#<xxx>
F
Freescale Semiconductor, Inc.
n
.