
8-8
ColdFire CF4e Core User’s Manual
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Local Memory Connection Specification
If the access address is mapped into the region defined by the SRAM (and this region is not
masked), it provides the data back to the processor and any cache or ROM data is discarded.
If the access address does not hit the SRAM, but is mapped into the region defined by the
ROM (and this region is not masked), the ROM provides the data back to the processor and
any cache data is discarded. Accesses from the SRAM and ROM modules are never cached.
The complete definition of the processor’s local bus priority scheme for read references is
as follows:
The internal processor memory hierarchy uses the following priority:
1. SRAM (highest)
2. ROM
3. Cache (if space is defined as cacheable)
4. External access (lowest)
8.4 Local Memory Connection Specification
This section describes the how memory devices are connected and how memory sizes are
configured.
8.4.1 K-Bus Memory Array Signal Connections
The processor supports the following six K-Bus processor local memory controllers:
The KRAM0 and KRAM1 (SRAM) memory controllers
the KROM0 and KROM1 (ROM) memory controllers
Instruction cache controller
Data cache controller.
Each controller supports a range of memory arrays, which must be synchronous SRAM or
ROM structures that use the same clock as the core. The following information details the
range of memory arrays supported and the necessary array connections.
8.4.1.1
KRAM Information
KRAM controllers use synchronous SRAM memory arrays external to the core. These
synchronous SRAMs must use the same clock as the core.
The KRAM controllers support a 32-bit array width (with byte write control) and array
sizes of 512 bytes and 1, 2, 4, 8, 16, 32, and 64 Kbytes. The controller uses the
kram{0,1}size[3:0] inputs to determine the connected array size, as shown in Table 8-2.
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