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參數(shù)資料
| 型號： | PowerPC 601 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 92/250頁 |
| 文件大小： | 916K |
| 代理商： | POWERPC 601 |
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3-20
PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors
When a data tenure overlaps its associated address tenure, a qualified ARTRY assertion
coincident with a DBG signal does not result in data bus mastership (DBB is not asserted).
Because the processor can pipeline outstanding data tenures when a new address tenure is
retried, the processor becomes data bus master to complete the previous transaction.
3.3.1.1 Effect of ARTRY Assertion on Data Transfer and Arbitration
on the PowerPC 604 Processor
The system designer must define the beginning of the window in which the snoop response
is valid and ensure that data is not transferred until one cycle before that window, or until
the same cycle as the beginning of that window in fast-L2 mode. The processors support a
snoop response window as early as two cycles after assertion of TS. In fast-L2 mode, data
cannot be transferred earlier than the first cycle of the assertion of ARTRY.
Asserting ARTRY can invalidate a previous or current data transfer and terminate the data
cycle, invalidate a qualified data bus grant, or cancel a future data transfer. The possible
scenarios are described as follows:
If data is transferred (via assertion of TA) two or more cycles before the beginning
of the snoop window in the normal mode, or one or more cycles before the beginning
of the snoop window in data streaming mode, then data is transferred too early to be
cancelled by ARTRY. Therefore, systems in which ARTRY can be asserted must not
attempt data transfers (assert TA) before this cycle.
If data is transferred in the cycle before the beginning of the snoop response window,
asserting ARTRY invalidates the data transfer in a similar fashion to assertion of
DRTRY except that the data tenure is aborted rather than extended. If data streaming
mode is active, data cannot be transferred in this cycle.
If data is transferred in the first cycle of the snoop response window, asserting
ARTRY invalidates the data transfer. This is like deasserting TA except that the data
tenure is aborted instead of continued.
If DBG has not been asserted, asserting ARTRY effectively negates the implied data
bus request associated with the address transfer, and the processor does not expect a
transfer. The system must not assert DBG for this transfer if any other processor data
transfers are pending.
If ARTRY is asserted during a data transfer, it is terminated after the first cycle of
ARTRY assertion. Therefore, a burst transfer can be cut short.
Asserting ARTRY in the same cycle as its corresponding DBG disqualifies the data
bus grant in that cycle so the 604 cannot start a data transaction on the following
cycle regardless of whether other data transactions are queued. However, on the
cycle after the ARTRY assertion, the 604 responds to a qualified data bus grant if it
has queued data transactions. Figure 3-8 shows a write address tenure that receives
an ARTRY snoop response in the same cycle the system asserts DBWO and DBG
(cycle 6) to grant the write data tenure before a previously-requested read data
tenure. Following the ARTRY assertion, the qualified DBG assertion to the
processor in cycle 7 is accepted for the read data tenure.
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