
5-10
PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors
5.3.2.2 Checkstop State (MSR[ME] = 0)—PowerPC 601 Processor
When a processor is in checkstop state, instruction processing is suspended and generally
cannot be restarted without resetting the processor. The contents of all latches are frozen
within two cycles upon entering checkstop state so that the state of the processor can be
analyzed as an aid in problem determination.
A machine check exception may result from referring to a nonexistent physical address. In
some implementations, for example, execution of a Data Cache Block Set to Zero (
dcbz
)
instruction that introduces a block into the cache associated with a nonexistent physical
address may delay the machine check exception until an attempt is made to store that block
to main memory.
Checkstop sources and enables for the 601 are described in the following section.
5.3.2.2.1 Checkstop Sources and Enables Register—HID0
The checkstop sources and enables register (HID0), shown in Figure 5-1, is a
supervisor-level register that defines enable and monitor bits for each of the checkstop
sources in the 601. The SPR number for HID0 is 1008.
Figure 5-1. HID0—Checkstop Sources and Enables Register (601)
Table 5-7 defines the bits in HID0. The enable bits (bits 15–31) can be used to mask
individual checkstop sources, although these are provided primarily to mask off any false
reports of such conditions for debugging purposes. Bit 0 (HID0[CE]) is a master checkstop
enable; if it is cleared, all checkstop conditions are disabled; if it is set, individual
conditions can be enabled separately. HID0[EM] (bit 16) enables and disables machine
check checkstops; clearing this bit masks machine check checkstop conditions that occur
when MSR[ME] is cleared. Bits 1–11 are the checkstop source bits, and can be used to
determine the specific cause of a checkstop condition.
All enable bits except 15 and 24 are disabled at start up. The operating system should enable
these checkstop conditions before the power-on reset sequence is complete.
Reserved
EDT
ESH
ECD
ETD
EBD
ECP
EIU
EPP
EBA
DRF
DRL
PAR
EMC
EHP
CE S
M TD CD SH DT BA BD CP IU PP
0 0 0
ES EM
LM
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31