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PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors
The 60x bus allows processors to access or otherwise communicate with other resources
that may share the bus, including system memory, secondary caches, I/O devices, bus
arbiters, and other devices. By and large, the 60x bus implementation is consistent among
the 601, 603, and 604; however, because the PowerPC architecture supports a broad range
of system implementations, each processor offers unique features.
Primary goals of this book are to provide the reader with an understanding of the operations
of the basic signals that are common to and required by all 60x processors as well as a
familiarity with those signals that are not common to all parts or required for basic
operation that can maximize the performance of a system implementation. To aid in this
understanding, this document focuses on the following bus relationships among current 60x
microprocessors:
General bus characteristics
Common bus characteristics
Differences between current implementations
This document specifically describes the communication signals and protocols used by the
601, 603, and 604, and does not describe the power, test, and clock signals. For that
information, refer to the particular 60x microprocessor user’s manual.
In this document, the terms ‘601’, ‘603’, ‘603e’ ‘604’, ‘604e’, and ‘60x bus’ are used as
abbreviations for ‘PowerPC 601 microprocessor’, ‘PowerPC 603 microprocessor’,
PowerPC 603e microprocessor’, ‘PowerPC 604 microprocessor’, PowerPC 604e
microprocessor’, and ‘PowerPC 60x microprocessor bus interface’, respectively. The terms
‘processor bus interface’ and ‘interface’ are analogous with the 60x bus.
To locate any published errata or updates for this document, refer to the world-wide web at
http://www.mot.com/powerpc/ or at http://www.chips.ibm.com/products/ppc.
Audience
This document is intended for system and processor hardware developers who are
developing products that incorporate or interface with the 60x microprocessors. It can also
benefit software developers who work with products that use these microprocessors.
Organization
Following is a summary and brief description of the major sections of this manual:
Chapter 1, “Overview,” is useful for readers wanting a general understanding of the
features and functions of the PowerPC processor interface. It defines various
operational subsets of these features and functions.
Chapter 2, “Signal Descriptions,” describes each processor input and output signal
and gives timing considerations.