
Chapter 5. System Status Signals
5-1
Chapter 5
System Status Signals
50
50
This chapter further describes the operation of the system status signals (interrupt,
checkstop, and reset signals) which are described in Section 2.9, “System Status Signals.”
Most of these are input signals that are used to generate asynchronous exceptions either as
a function of normal system operations or as the result of an error. This chapter also briefly
discusses asynchronous exceptions described in
The
Programming Environments Manual
,
with particular attention given to differences in how 60x processors implement those
exceptions.
5.1 Overview
The PowerPC 601, 603, and 604 processors implement asynchronous exceptions that are
triggered by signals. Asynchronous exceptions can be either maskable or nonmaskable.
Table 5-1 lists the signal-triggered operations implemented in the 60x processors. (The
only other architecture-defined asynchronous exception, the decrementer exception, is
triggered internally.) The table shows the event priority and indicates whether a related
exception is maskable and precise.
Table 5-1. Resets, Interrupts, and Their Sources
Resets/
Interrupts
Maskable/
Nonmaskable
Precise/
Imprecise
Priority
Source
601
603
604
Hard reset
Nonmaskable
Imprecise
Highest priority
HRESET HRESET
HRESET
Machine
check
Nonmaskable
Imprecise
Second-highest priority
TEA
TEA, MCP,
APE, DPE
TEA, MCP,
APE, DPE
Soft reset
Nonmaskable
Imprecise
Third-highest priority
SRESET SRESET
SRESET
System
management
*
Maskable
Precise
Lower priority than synchronous
exceptions; higher than external
interrupt.
—
SMI
SMI
External
interrupt
Maskable
Precise
Lower priority than a system
management exception; higher
than decrementer exception.
INT
INT
INT
*
The system management exception is not defined by the PowerPC architecture, but is implemented similarly in
several PowerPC processors.