
Chapter 7. Direct-Store Interface
7-9
Figure 7-6. Direct-Store Interface Store Access Example
If TEA is asserted during a direct-store access, the resulting action is delayed until all data
transfers from the direct-store access complete. The device asserting TEA must keep it
asserted until the last direct-store data tenure is complete. The direct-store reply, in cases of
TEA assertion, is not required and is ignored by the processor. The processor does not
recognize the assertion of TEA until the last direct-store data tenure completes.
7.6 Memory-Forced Direct-Store Interface
(PowerPC 601 Processor Only)
The 601 defines two types of direct-store segments (segment register T bit set) based on the
value of the BUID, as follows:
Direct-store interface (BUID
≠
0x07F)—Normal direct-store accesses include all
transactions between the 601 and BUCs mapped through direct-store address space.
Memory-forced direct-store interface (BUID = 0x07F)—Memory-forced direct-
store interface operations access memory space. They do not use the extensions to
the memory protocol described for direct-store accesses, and they bypass the page-
and block-translation and protection mechanisms. The physical address is found by
concatenating bits 28–31 of the respective segment register with bits 4–31 of the
effective address. This address is marked noncacheable, write-through, and global.
Because memory-forced direct-store accesses address memory space, they are
subject to the same coherency control as other memory reference operations. More
generally, accesses to memory-forced direct-store segments are considered to be
cache-inhibited, write-through, and memory-coherent operations with respect to the
601 cache and bus interface.
ABB
XATS
ADDR+XATC
DBB
DH[0–31]
TA
1
2
3
4
5
6
7
8
9
10
PKT 0
PKT 1
PKT 0
PKT 1
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