
2-24
PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors
2.7.4 Data Bus Parity (DP[0–7])—Input
Following are state and timing descriptions for DP[0–7] as input signals.
State Meaning
Asserted/Negated—Represents one bit of odd parity for each byte of
read data. Parity is checked on all data byte lanes during data read
operations, regardless of the size of the transfer. During direct-store
read operations, only the DP[0–3] signals (corresponding to byte
lanes DH[0–31]) are checked for odd parity. If data parity errors are
enabled, detected even parity causes a checkstop or a machine check
exception (and assertion of DPE) depending on the state of
MSR[ME]. For the 601, if data parity check is enabled in HID0,
detection of even parity unconditionally causes a checkstop.
Timing Comments
Assertion/Negation—The same as DL0–DL31.
2.7.5 Data Parity Error (DPE)—Output
Following are state and timing descriptions for the data parity error (DPE) output signal.
DPE is an open-drain type output and requires a pull-up resistor for proper deassertion.
State Meaning
Asserted—The processor detected incorrect data bus parity on
incoming read data.
Negated—Indicates correct data bus parity.
Timing Comments
Assertion—Occurs on the second bus clock cycle after TA is asserted
to the processor and is driven for one cycle.
2.7.6 Data Bus Disable (DBDIS)—Input
Following are the state meanings and timing comments for the data bus disable (DBDIS)
input signal. This signal is not on the 601.
State Meaning
Asserted—For a write transaction, the processor must release the
data bus and DP[0–7] to high impedance in the next cycle. The data
tenure remains active, DBB remains driven, and the transfer
termination signals are still monitored by the processor. The DBDIS
signal is ignored for read transactions.
Negated—The data bus should remain normally driven.
DP4
DL[0–7]
DP5
DL[8–15]
DP6
DL[16–23]
DP7
DL[24–31]
Table 2-7. DP[0–7] Signal Assignments (Continued)
Signal Name
Signal Assignments