
Chapter 7. Direct-Store Interface
7-1
Chapter 7
Direct-Store Interface
70
70
Accesses to direct-store segments, as defined in the PowerPC architecture, are executed on
the bus using the extended transfer protocol (ETP), an extension to the basic transfer
protocol described in previous chapters. Except for one signal, XATS, this protocol uses the
same signal set as the basic transfer protocol, although some signals are redefined. The
PowerPC 601 processor documentation refers to the direct-store interface as the I/O
controller interface.
Direct-store operations are no longer required by the PowerPC architecture. Some
processors, such as the PowerPC 603e processor, do not support this feature.
PowerPC architecture defines the following characteristics for direct-store accesses:
The extended address delivered to the I/O system includes a bus unit ID (BUID) to
address one of several bus devices and a 32-bit address to be delivered to each.
A transaction error can be detected and associated with the original instruction.
To satisfy the requirements of PowerPC architecture for direct-store segments, the
following extensions are implemented:
A new set of bus operations is provided that redefines how the transfer type (TT
n
),
transfer burst (TBST), and transfer size (TSIZ
n
) signals are used. These signals
together generate the extended address transfer code (XATC), as shown in
Table 7-4.
Each direct-store address transfer takes two beats. The first transmits the BUID and
several control bits from the segment register, and the second transfers a complete
32-bit address to the slave device.
Explicit sender/receiver tags are provided.
A split-response protocol is enforced; that is, the sender must wait for a reply from
the receiver before considering a transaction complete.
The 60x does not burst direct-store transactions, but a type of streaming is permitted.
Streaming (in this context) allows multiple single-beat transactions to occur before
a reply from the direct-store receiver is required.