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參數(shù)資料
| 型號： | PowerPC 604 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 203K |
| 代理商： | POWERPC 604 |
The Effect of Solder-Joint Temperature Rise on Ceramic-Ball-Grid Array to Board
Interconnection Reliability: The Motorola PowerPC 603 and PowerPC 604
Microprocessors and MPC105 Bridge/Memory Controller
R. David Gerke
Gary B. Kromann
m
Advanced Packaging Technology
6501 William Cannon Dr., OE55
Semiconductor Products Sector,
Austin, Texas 78735
ABSTRACT
To predict solder joint reliability of surface-mount
technology, a key parameter is: the temperature rise above
ambient at the solder joint,
T. In-situ field temperature
measurements were taken for a range of computer
platforms in an office environment, at the central-
processing units. Printed-circuit boards (PCB) were not
uniform, therefore only maximum temperature regions of
the board were measured. These maximum temperatures
revealed the mean to be less than 20
°
C above ambient (i.e.,
T < 20
°
C) regardless of the power of the device. The
largest
T measured in any system was less than 30
°
C
above ambient.
These temperature measurements of actual
computer systems are in close agreement with IPC-SM-
785. By utilizing the measured PCB temperature rise,
solder joint fatigue life was calculated for the 21mm
ceramic ball-grid-array (CBGA), the package for the
PowerPC 603 and PowerPC 604 RISC
microprocessors. For the MPC105 PCI Bridge/Memory
Controller package, data from both the 21mm and 25mm
CBGA, were used for the estimate . At an average on-off
T of 20
°
C, the 21mm CBGA and the 21 x 25mm CBGA
have an estimated fatigue life of over 25 years and over 20
years; respectively.
NOMENCLATURE
M a i n V a r i a b l e s
AF
Tmax
T
f
= acceleration factor
= highest Ton temperature (K)
= Ton - Toff
= thermal cycling frequency; # of cycles
must be at least 6 per day
S u b s c r i p t s
l
= lab conditions
f
= field conditions
INTRODUCTION
PowerPC 603 and PowerPC 604 Microprocessors and
MPC 105 Bridge/Memory Controller
The scaleable PowerPC microprocessor family, jointly
developed by Apple, IBM, and Motorola, is being designed
into high-performance cost-effective computers (including
notebooks, desktops, workstations, and servers). The
PowerPC 603 microprocessor is a low-power imple-
mentation of the PowerPC Reduced Instruction Set
Computer architecture. The PowerPC 604 microprocessor
is a 32-bit implementation of the PowerPC architecture,
and is software and bus compatible with the PowerPC
601 and PowerPC 603 microprocessors. Both devices
may be offered in a 21mm controlled-collapsed-chip-
connection/ceramic-ball-grid array (C4/CBGA) (Figure 1).
The MPC105 PCI Bridge/Memory Controller provides a
PowerPC Reference Platform (PReP) compliant bridge
between PowerPC 603 or PowerPC 604 RISC micro-
processors and the Peripheral Component Interconnect
(PCI) bus. The MPC105 integrates secondary control and
a high-performance memory controller that supports
DRAM, SDRAM, ROM, and Flash ROM. The MPC105
uses an advanced, 3.3 volt CMOS process technology and
is packaged in a 21 by 25 mm (16 x 19 ball matrix)
C4/CBGA.
Chip w/C4
Encapsulant
PCB
CBGA joint
Ceramic Substrate
Figure 1.
C4 Ceramic-Ball-Grid Array: Cross-sectional
View (not to scale)
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