
Chapter 4. Memory Coherency
4-17
Figure 4-8. Effective Address Bits in Bus Address
When the TLBIE appears on the bus, attached 60x processors invalidate the congruence
class of the TLB that corresponds to the transmitted bits of the effective address.
4.7.10 SYNC
SYNC is an address-only transaction that a 60x processor places onto the bus as the result
of execution of a
sync
instruction. If a processor has other snooped cache operations
pending when it detects a SYNC on the bus, it asserts ARTRY. A 601 detecting a SYNC on
the bus also asserts ARTRY for any pending operations based on an invalidated TLB.
The 603 does not broadcast or snoop SYNC.
4.7.11 TLBSYNC
TLBSYNC is an address-only transaction placed on the bus by execution of a
tlbsync
instruction or a pending TLBIE bus operation. A 604 seeing
tlbsync
, asserts ARTRY if any
pending operations are based on an invalidated TLB.
The 603 does not broadcast or snoop TLBSYNC operations. The 601 does not implement
the
tlbsync
instruction and does not generate this bus operation.
4.7.12 EIEIO
The EIEIO bus operation is generated by executing an
eieio
instruction, which acts as a
fence in the instruction flow to enforce ordered execution of accesses to noncacheable
memory. The 60x processors internally enforce ordering of such accesses with respect to
the
eieio
, in the sense that noncacheable accesses due to instructions that occur before the
eieio
in the program order are placed on the bus before any noncacheable accesses that
result from instructions that occur after the
eieio
, with the EIEIO bus operation separating
the two sets of bus operations.
If the system implements any mechanism that allows reordering of noncacheable requests,
then the appearance of an EIEIO should cause it to force ordering between accesses that
occurred before and those that occur later.
The 603 does not broadcast or snoop EIEIO operations.
Bus Address
0
12
19
31
Bits from EA