
Chapter 1. Overview
1-7
Data bus busy (DBB)
√ √
Indicates the data bus is busy
√
2.6.4
Data Transfer Signals
Data bus
(DH[0–31];DL[0–31])
√ √
Represents the data being transferred
√
2.7.1
2.7.2
Data bus parity (DP[0–7])
√ √
Represents odd parity for the data bytes
√
2.7.3
2.7.4
Data parity error (DPE)
√
Forces processor to put data bus in high-
impedance state during a write data tenure;
other processor operations are unaffected.
√
2.7.5
Data bus disable (DBDIS)
√
Indicates to the processor that a write
transaction should be stopped
√
2.7.6
Data Transfer Termination Signals
Transfer acknowledge (TA)
√
Indicates that a single-beat data transfer
completed successfully
√
2.8.1
Data retry (DRTRY)
√
Invalidates read data sent to processor with TA
in the previous cycle. On hard reset, is used to
configure some alternate modes.
√
2.8.2
Transfer error
acknowledgment (TEA)
√
Indicates that a bus error occurred
√
2.8.3
System Status Signals
Interrupt (INT)
√
Indicates an external interrupt to the processor
√
2.9.1
System management
interrupt (SMI)
√
Indicates a system management interrupt to the
processor
√
2.9.2
Machine check (MCP)
√
Indicates a machine check exception
√
2.9.3
Checkstop input
(CKSTP_IN)
√
Indicates the processor must stop operation
(checkstop)
√
2.9.4
Checkstop output
(CKSTP_OUT)
√
Indicates the processor has detected a
checkstop condition
√
2.9.5
Hard reset (HRESET)
√
Initiates a hard reset exception
√
2.9.6
Soft reset (SRESET)
√
Initiates a soft reset exception
√
2.9.7
Processor State Signals
Reservation (RSRV)
√
Indicates that a reservation generated by a
lwarx
instruction exists in the processor
√
2.10.1
External cache
intervention (L2_INT)
√
Indicates intervention from other bus masters
√
2.10.2
Time base enable (TBEN)
√
Indicates the time base should continue clocking
√
2.10.3
Table 1-2. Use and Reference for Bus Signals (Continued)
Signal
I
O
Function
Application
Section
Basic L2 MP Opt.