
Contents
vii
CONTENTS
Paragraph
Number
Title
Page
Number
4.7.14
4.7.15
4.8
4.9
4.10
Read with No Intent to Cache (RWNITC).....................................................4-18
XFERDATA ..................................................................................................4-18
External WIM Bit Settings.................................................................................4-19
Direct-Memory Access and Memory Coherency...............................................4-19
Overview of Implementation Differences..........................................................4-19
Chapter 5
System Status Signals
5.1
5.2
5.2.1
5.2.1.1
5.2.2
5.2.2.1
5.2.2.2
5.2.2.3
5.2.2.4
5.3
5.3.1
5.3.2
5.3.2.1
Overview..............................................................................................................5-1
Resets ...................................................................................................................5-2
Hard Reset and Power-On Reset......................................................................5-3
Hard Reset Settings......................................................................................5-3
Soft Reset.........................................................................................................5-5
System Reset Exception (0x00100).............................................................5-5
Soft Reset on the PowerPC 601 Microprocessor.........................................5-6
Soft Reset on the PowerPC 603 Microprocessor.........................................5-7
Soft Reset on the PowerPC 604 Microprocessor.........................................5-7
Machine Check and Checkstops ..........................................................................5-7
Checkstop State (MSR[ME] = 0).....................................................................5-7
Machine Check Exception (0x00200)..............................................................5-8
Machine Check Exception (0x00200)—
PowerPC 601 Processor...........................................................................5-9
Checkstop State (MSR[ME] = 0)—PowerPC 601 Processor....................5-10
Checkstop Sources and Enables Register—HID0.................................5-10
Machine Check Exception—PowerPC 603 Processor...............................5-12
Checkstop State (MSR[ME] = 0)—PowerPC 603 Processor....................5-13
Machine Check Exception—PowerPC 604 Processor...............................5-13
Machine Check Exception Enabled (MSR[ME] = 1)............................5-14
Checkstop State (MSR[ME] = 0)...........................................................5-14
External Interrupt Exception (0x00500) ............................................................5-14
External Interrupt—PowerPC 601 Processor.................................................5-15
External Interrupt—PowerPC 603 Processor.................................................5-16
System Management Interrupt Exception (0x01400) ........................................5-16
5.3.2.2
5.3.2.2.1
5.3.2.3
5.3.2.4
5.3.2.5
5.3.2.5.1
5.3.2.5.2
5.4
5.4.1
5.4.2
5.5
Chapter 6
Additional Bus Configurations
6.1
6.1.1
6.2
6.2.1
No-
DRTRY
No-DRTRY Mode in PowerPC 604e Processor..............................................6-2
Data Streaming Mode (604).................................................................................6-3
Data Valid Window in the Data Streaming Mode...........................................6-3
Mode (603 and 604e).......................................................................6-1