
Chapter 2. Signal Descriptions
2-31
2.11 Power Management Signals
Each processor has input and output signals defined to support low-power modes for the
processor and system. These signals are not the same between processors. The signals for
each processor are described in this section.
2.11.1 Quiescent Request (QUIESC_REQ)—Output
Following are state and timing descriptions for the quiescent request (QUIESC_REQ)
output signal, which the 601 uses to request the system to enter a soft-stop state.
State Meaning
Asserted—The 601 is requesting a soft stop state for the system.
Negated—The 601 is not requesting a soft stop state.
Assertion/Negation—May occur at any time.
Timing Comments
2.11.2 System Quiesced (SYS_QUIESC)—Input
Following are state and timing descriptions for the system quiesced (SYS_QUIESC) input
signal which the system uses to indicate to the 601 that it is ready to enter the soft-stop state.
State Meaning
Asserted—Enables soft stop in the 601.
Negated—The soft-stop state is not enabled in the 601. Systems that
do not use SYS_QUIESC should tie it low.
Assertion/Negation—Must meet setup and hold times described in
the
PowerPC 601 RISC Microprocessor Hardware Specifications
.
Timing Comments
2.11.3 Resume (RESUME)—Input
Following are state and timing descriptions for the RESUME input signal, which the
system uses to indicate to the 601 that it can resume normal operations.
State Meaning
Asserted—The 601 can resume normal operations after a soft stop.
Negated—The 601 cannot resume normal operations if a soft stop
has occurred. Systems that do not use this signal should tie it low.
Assertion—Can occur any time. If asserted asynchronously to the
601 input clock, it must be asserted for at least three clock cycles. If
asserted synchronously, it must be asserted at least two clock cycles.
Negation—Can occur after the minimum pulse width has been met.
Timing Comments