
Chapter 5. System Status Signals
5-11
Table 5-7. HID0—Checkstop Sources and Enables Register (601)
Bit
Name
Description
0
CE
Master checkstop enable. Enabled if set. If this bit is cleared and the TEA signal is asserted, a
machine check exception is taken, regardless of the setting of MSR[ME].
1
S
Microcode checkstop detected if set.
2
M
Double machine check detected if set.
3
TD
Multiple TLB hit checkstop if set.
4
CD
Multiple cache hit checkstop if set.
5
SH
Sequencer time out checkstop if set.
6
DT
Dispatch time out checkstop if set.
7
BA
Bus address parity error if set.
8
BD
Bus data parity error if set.
9
CP
Cache parity error if set.
10
IU
Invalid microcode instruction if set.
11
PP
Direct-store interface access protocol error if set.
12–14
—
Reserved
15
ES
Enable microcode checkstop. Enabled by hard reset. Enabled if set.
16
EM
Enable machine check checkstop. Disabled by hard reset. Enabled if set. If this bit is cleared
and the TEA signal is asserted, a machine check exception is taken, regardless of the setting
of MSR[ME].
17
ETD
Enable TLB checkstop. Disabled by hard reset. Enabled if set.
18
ECD
Enable cache checkstop. Disabled by hard reset. Enabled if set.
19
ESH
Enable sequencer time out checkstop. Disabled by hard reset. Enabled if set.
20
EDT
Enable dispatch time out checkstop. Disabled by hard reset. Enabled if set.
21
EBA
Enable bus address parity checkstop. Disabled by hard reset. Enabled if set.
22
EBD
Enable bus data parity checkstop. Disabled by hard reset. Enabled if set.
23
ECP
Enable cache parity checkstop. Disabled by hard reset. Enabled if set.
24
EIU
Enable for invalid ucode instruction checkstop. Enabled by hard reset. Enabled if set.
25
EPP
Enable for direct-store protocol checkstop. Disabled by hard reset. Enabled if set.
26
DRF
0
1
Optional reload of alternate sector on instruction fetch miss is enabled.
Optional reload of alternate sector on instruction fetch miss is disabled.
27
DRL
0
1
Optional reload of alternate sector on load/store miss is enabled.
Optional reload of alternate sector on load/store miss is disabled.
28
LM
0
1
Big-endian mode is enabled.
Little-endian mode is enabled.
29
PAR
0
1
Precharge of the ARTRY and SHD signals is enabled.
Precharge of the ARTRY and SHD signals is disabled.