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參數(shù)資料
| 型號(hào)： | PowerPC 601 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁(yè)數(shù)： | 148/250頁(yè) |
| 文件大小： | 916K |
| 代理商： | POWERPC 601 |
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6-4
PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors
In data streaming mode, the data buffering that allows late cancellation of a data transfer
does not exist, so late cancellation with ARTRY is also impossible. Therefore, the earliest
that data can be transferred in data streaming mode is the first cycle of the ARTRY window,
not the cycle before that.
6.2.3 Design Practices for Data Streaming Mode
It is recommended that use of data streaming mode be accompanied by two other system
design practices:
Do not use ABB. If the system is designed so an address tenure is defined by TS and
AACK assertion, (which the 604 is designed to support), ABB is unnecessary and
should be pulled high at the 604. Because ABB has a short restore-high time, ABB
should not be used in systems that try to achieve a short cycle time.
Do not use DBB, which is restored high in the same way as ABB and therefore has
the same problems in a system with short cycle times. To avoid using DBB, the
system arbiter must assert DBG for a single cycle, one cycle before the 604 is
supposed to begin its data tenure. The DBB signal should be pulled high. The
additional system cost of operating in this manner is that data transfers must be
counted and DBG can be asserted only on the last cycle in a data tenure.
6.3 32-Bit Data Bus Mode (603)
The 603 supports an optional 32-bit data bus mode, which operates like the 64-bit data bus
mode but uses only byte lanes 0–3, corresponding to DH[0–31] and DP[0–3]. Byte lanes
4–7 (DL[0–31] and DP[4–7]) are never used in this mode. Unused bus signals are ignored
during read operations and are driven low for write operations.
In 32-bit bus mode, data tenures can be one, two, or eight beats depending on the size of
the program transaction and the cache mode for the address. Data transactions of one or two
data beats are performed for caching-inhibited load/store or write-through store operations.
Note that two-beat burst transactions do not assert TBST (having the same TBST and
TSIZ[0–2] encodings as the 64-bit data bus mode).
Single-beat data transactions transfer four bytes or less, and two-beat data transactions are
performed for eight-byte operations only. The 603 generates an eight-byte operation only
for a double-word–aligned load double or store double operation to or from the floating-
point registers (FPRs).
Eight-beat burst data transactions load data into or store data from the 603’s internal caches.
These transactions transfer 32 bytes in the same way as in 64-bit data bus mode, asserting
TBST and signalling a transfer size of 2 (TSIZ[0–2] = 0b010).
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