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| 型號(hào)： | PowerPC 601 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁(yè)數(shù)： | 115/250頁(yè) |
| 文件大?。?/td> | 916K |
| 代理商： | POWERPC 601 |
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Chapter 4. Memory Coherency
4-9
When a processor is not the address bus master, GBL is an input. The 604 snoops a
transaction if TS and GBL are asserted together in the same bus clock cycle (this is a
qualified snooping condition). No snoop update to the 604 cache occurs if the snooped
transaction is not marked global. This includes invalidation cycles.
When the processor detects a qualified snoop condition, the address associated with the TS
is compared against the data cache tags through a dedicated cache tag port. Snooping
completes if no hit is detected. If, however, the address hits in the cache, the processor
reacts according to the MESI protocol shown in Figure 4-6, assuming the WIM bits are set
to write-back mode, caching allowed, and coherency enforced (WIM = 001).
Write hits to modified cache blocks of nonglobal pages do not generate invalidate
broadcasts. Several bus transactions involve moving data that can no longer access the TLB
M bit (for example, replacement cache block copy-back or a snoop push). In these cases,
because hardware cannot determine whether the cache block was originally marked global,
the processor marks these transactions as nonglobal to avoid retry deadlocks.
See Table 4-2 for the CSE[0–1] encodings for the 604.
4.4 Coherency Timing
60x processors communicate the results of their snooping over the snoop response lines,
ARTRY and SHD. These signals are defined to be valid at least the cycle after assertion of
AACK. A 60x that tries to acquire a memory block is considered to have acquired it after
it has successfully completed the address tenure requesting the data (no-ARTRY
indication). After that cycle, it snoops for that address. Likewise, a 60x processor that is
flushing data from its cache is considered to have completed the transfer from the
standpoint of memory coherency after it has successfully completed the address tenure for
the push or copy-back. Once this has occurred, it no longer snoops for this address.
Note that this has implications to system design. For example, after a 60x pushes a cache
block, it may be some time before the block is actually stored in memory. If a read of the
same block occurs after the push address tenure is completed, it is not snooped by the 60x
performing the push. The system must ensure that proper ordering is maintained so that the
correct data is read.
4.5 Coherency Protocol
The 60x bus supports a four-state (MESI) cache coherency protocol through the use of
address retry (see Figure 4-6). The 601 and 604 implement the protocol to the extent
required to support multiprocessor systems. Because it does not support the shared state,
the 603 supports a three-state subset of the MESI protocol, (MEI) protocol, which assures
coherency in a a single-processor system. All references to the shared state do not apply to
the 603.
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