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參數(shù)資料
| 型號(hào)： | PowerPC 601 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁(yè)數(shù)： | 76/250頁(yè) |
| 文件大?。?/td> | 916K |
| 代理商： | POWERPC 601 |
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3-4
PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors
Processors can generate address-only bus operations during execution of certain
instructions (for example
dcbz
,
sync
,
eieio
,
tlbie
, and
lwarx
). Address-only operations are
given more support on processors intended for multiprocessor systems. The ability to retry
address tenures provides an efficient snooping protocol for maintaining coherency in
systems with multiple memory systems (including caches).
Although address and data transfers are separate, there is no explicit tagging mechanism to
associate a data transfer with its address transfer. Addresses and data are generally
transferred in the same order. However, the data bus write only (DBWO) signal allows
writes to transfer ahead of reads. The designer of a multiple processor system can provide
any ordering, as long as each processor transfers its addresses and data in same order and
memory is kept coherent.
3.1.1 Arbitration Signals
Arbitration for both address and data bus mastership is performed by a central, external
arbiter and minimally by the arbitration signals shown in Section 2.1, “Address Bus
Arbitration Signals,” and Section 2.6, “Data Bus Arbitration Signals.” Most arbiter
implementations require additional signals to coordinate bus master/slave/snooping
activities. Note that address bus busy (ABB) and data bus busy (DBB) are bidirectional
signals. They are processor inputs unless it is master of one or both buses; they must be
connected high through pull-up resistors so that they remain negated when no devices have
control of the buses. Table 3-1 shows the bus arbitration signals.
Address bus arbitration signals are described as follows:
BR (bus request)—Assertion indicates that a device wants address bus mastership.
BG (bus grant)—Assertion indicates the device can, with the proper qualification,
take mastership of the address bus. See Section 2.1.2, “Bus Grant (BG)—Input.”
ABB (address bus busy)—Assertion identifies the address bus master.
Table 3-1. Number of Bus Arbitration Signals
Signal
I/O
Signal Connection Requirements
BR
Output
One per master
BG
Input
One per master
ABB
Both
Common among masters
DBG
Input
One per master
DBWO
Input
One per processor
DBB
Both
Common among masters (one per master if data streaming is used across multiple masters)
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