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參數(shù)資料
| 型號(hào)： | PowerPC 601 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁(yè)數(shù)： | 180/250頁(yè) |
| 文件大小： | 916K |
| 代理商： | POWERPC 601 |
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D-2
PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors
Simple L1 inclusion—L1 inclusion requires that an address cannot be in the L1
cache unless it is in the L2 cache. Ensure that the contents of the L1 cache are a
subset of the contents of the L2 cache.
Marked L1 inclusion—In addition to guaranteeing inclusion, marked inclusion
keeps more information about when an L2 cache entry is also in the L1 cache. The
advantages of marked L1 inclusion over simple L1 inclusion include being able to
do a better job of snoop filtering and reducing the amount of back invalidations.
For each of these approaches (except the simplest case of performing no snoop filtering),
each description includes the following:
Requirements for saving state information—Information about the kind and amount
of state information that must be maintained.
Operations required for processor bus operations—Information regarding
operations that are necessary to maintain consistency between the L1 and L2 caches.
System bus operation forwarding to the processor—A description of the system bus
operations must be passed to the processor for each configuration.
Note that the prefix SYS distinguishes system bus signals from 60x signals with the same
name. For example, the system bus counterpart to the 60x signal SHD is SYS-SHD.
D.1 Unfiltered Snooping
The simplest way to design in an L2 cache is to not filter snoop operations. The L2 cache
responds to snoop requests from the system bus after first passing the snoop request through
to the L1 cache.This following design issues should be considered:
If the processor’s L1 cache has a second tag port dedicated to snooping, the
processor is not stalled for unnecessary snoops. This is true for the 601 and 604 but
not for the 603.
The time the external address bus is busy with unnecessary snoops is not a
significant portion of the address bandwidth required by the processor. A
multiprocessor system cannot meet this condition practically; however, a
single-processor system can meet the condition if DMA address bandwidth is low.
D.2 Keeping a Copy of L1 Tags
Keeping a copy of the L1 tags in the L2 cache allows a system address to be compared
against the L1 tags and the L2 tags in parallel. If neither directory matches, the
processor/L2 cache complex is not involved in the current bus transaction and does not need
to intervene. Typically, intervention implies assertion of either SYS-ARTRY or SYS-SHD.
If only the L2 tag matches, the L2 cache must intervene. If an L1 tag matches, the system
address must be passed to the processor so it can respond. After the processor responds and
completes any necessary snoop response, the system bus operation can be rerun against the
possibly-changed state of the L2 cache.
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