
Chapter 2. Signal Descriptions
2-3
Note that the 601 recognizes a qualified bus grant on the cycle after
AACK even if ARTRY is asserted as long as the 601 is asserting
ARTRY and has exclusive ownership of the data associated with the
snoop that caused the ARTRY. The ABB and ARTRY signals are
driven by the bus master. If the processor is parked, BR need not be
asserted for the qualified bus grant.
Negated—The device is not the next potential address bus master.
Assertion—May occur at any time to indicate the device is free to
use the address bus. After the processor gains bus mastership, it does
not check for a qualified bus grant again until the cycle in which the
address bus tenure completes (assuming it has another transaction to
run). The processor does not accept a BG in the cycles between the
assertion of any TS or XATS through to the assertion of AACK.
Negation—May occur at any time to indicate the device cannot use
the bus. However, the device still assumes mastership on the bus
clock cycle BG is negated because, in the previous cycle, BG
indicated to the device that it could take mastership (if qualified).
Timing Comments
2.1.3 Address Bus Busy (ABB)—Output
Following are state and timing descriptions for address bus busy (ABB) as an output signal.
State Meaning
Asserted—The device is the address bus master.
Negated—The device is not using the address bus. If ABB is negated
in the bus clock cycle after a qualified bus grant, the device did not
accept mastership, even if BR was asserted. This can occur if a
potential transaction is aborted internally before it started.
Timing Comments
Assertion—Occurs on the bus clock cycle after a qualified bus grant
that is accepted by the device (see Negated).
Negation—Occurs for a fraction of the bus clock cycle after AACK
is asserted. If ABB is negated in the bus clock cycle after a qualified
BG, the device did not accept mastership, even if BR was asserted.
High Impedance—Occurs during a fractional portion of the bus
cycle in which ABB is negated. ABB is guaranteed by design to be
high impedance by the end of the cycle in which it is negated. For
specific information, see the particular processor’s user’s manual.