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參數(shù)資料
| 型號(hào)： | PowerPC 601 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁(yè)數(shù)： | 184/250頁(yè) |
| 文件大?。?/td> | 916K |
| 代理商： | POWERPC 601 |
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D-6
PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors
D.3.3 Forwarding System Bus Operations to the Processor
If an L1 tag entry was marked as S, for system read operations (a fairly common
occurrence) the L2 controller can directly respond with the SYS-SHD signal without
requiring an access to the processor’s cache. This not only reduces processor-to-L2 address
bus interference, it also improves the system bus bandwidth, as the system bus operation
would not need to be retried during interrogation of the processor’s L1 cache. Whenever the
L1 tag state is E or whenever something other than a simple read operation is performed on
the system bus, the operation passes to the processor to determine the final outcome.
D.4 Simple L1 Inclusion
L1 inclusion requires that when an address is not in the L2 cache, it is also not in the L1
cache. Although this functionally is the same as saying that an address cannot be in the L1
cache unless it is in the L2 cache, the first definition more closely reflects how L1 inclusion
is implemented.
The simplest approach to L1 inclusion in an L2 cache is to require that whenever something
is discarded from the L2 cache, to ensure that it is also discarded from the L1 cache through
a back invalidation. In this discussion, the L2 cache is assumed to use four-state MESI
protocol. Simplifications to a three-state protocol are trivial.
D.4.1 Requirements for Saving State Information
Simple L1 inclusion requires the same tags and state as is needed to implement the L2. Note
that the state information can be kept across the L2 cache block or per-coherency granule.
D.4.2 Operations Required for Processor Bus Operations
The operations performed and monitored to maintain L1 inclusion are like those required
for maintaining L1 tags (See Section D.3.2, “Operations Required for Processor Bus
Operations.”) However, as is discussed below, there is no need to be concerned with the
indication that a copy-back buffer is being used.
When an allocation is performed by the L1 cache, the L2 cache must also ensure that a tag
is allocated. Before allocation of a tag in the L2, a back invalidation (flush block or
RWITM) for each coherency granule removed must be sent to the processor. These back
invalidations cause either a snoop miss or hit.
For a snoop miss, the L1 cache has replaced that entry (either previously or for the current
allocation) and no further work is needed. Only when snoop push-backs required for all
removed granules are completed can the old tag be removed from the L2 directory and the
fetch for the new tag begin. The replacement of a tag from the L2 may itself require a
copy-back to main memory. Whether the copy-back is buffered is independent from the
maintenance of the inclusion.
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