
Chapter 7. Direct-Store Interface
7-3
7.1.1 Packet 0
Figure 7-2 shows the organization of the first packet in a direct-store transaction. The
XATC contains the transfer code. The address bus contains the following:
Key bit || segment register || sender tag
Figure 7-2. Direct-Store Operation—Packet 0
The contents of the address bus are described in Table 7-1.
Table 7-1. Address Bits for Packet 0
Bits
Description
0–1
Reserved. These bits should be cleared for compatibility with future PowerPC microprocessors.
2
Key bit—either SR[Kp] or SR[Ks]. Kp indicates user-level access and Ks indicate supervisor-level access.
The processor multiplexes the correct key bit into this position according to the operating context.
3–27
Address bits 3–27 correspond to bits 3–27 of the selected segment register. A[3–11] form the receiver tag
(BUID). Software must initialize these SR bits to the ID of the BUC to be addressed. The 601 supports an
additional mode, memory-forced direct-store mode, not defined by the PowerPC architecture, and
dependent on the value of BUID. See Section 7.6, “Memory-Forced Direct-Store Interface (PowerPC 601
Processor Only).”
28–31
PID (sender tag)—Allows a maximum of 16 processor IDs to be defined for a given system. If more bits
are needed for a very large multiprocessor system, the L2 cache (or equivalent logic) can append a larger
processor tag. The BUC addressed by the receiver tag should latch the sender address required by the
subsequent I/O reply operation.
The 601 and 604 PID comes from PID [28–31]. The 603 PID is always driven as 0b0000.
I/O Transfer Code
0
1 2 3
1112
27 28
31
0
7
A[0–31] + Attributes
Address Bus (A[0–31])
PKT 0 PKT 1
+
XATC
Reserved
Key Bit
From Segment Register
BUID
PID