Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
43
4 Hardware Architecture
(continued)
4.6 Triport Random-Access Memory (TPRAM)
Each core has a private block TPRAM (TPRAM0 and TPRAM1) each consisting of 96 banks (banks 0—95) of zero
wait-state memory. Each bank consists of 1K 16-bit words and has three separate address and data ports—one
port to the core’s instruction/coefficient (X-memory) space, a second port to the core’s data (Y-memory) space, and
a third port to the DMAU’s (Z-memory) space. TPRAM is organized into even and odd interleaved banks for which
each even/odd address pair is a 32-bit wide module as illustrated in
Figure 10
. The core’s data buses (XDB and
YDB) and the DMAU’s data bus (ZIDB) are each 32 bits wide, and therefore 32-bit data in the TPRAM with an
aligned (even) address can be accessed in a single cycle. Typically, a misaligned double word is accessed in two
cycles.
Figure 10. Interleaved Internal TPRAM
Figure 11
illustrates an example arrangement of single words (16 bits) and double words (32 bits) in memory. It
also illustrates an aligned double word and a misaligned double word. See the DSP16000 Digital Signal Processor
Core Information Manual for details on word alignment and misalignment wait-states.
Example Memory Arrangement
Figure 11. Example Memory Arrangement
0x000
0x003
0x001
0x002
0x7FF
0x7FE
11 LSBs
OF
ADDRESS
16 bits
16 bits
32 bits
EVEN BANK
ODD BANK
11 LSBs
OF
ADDRESS
TPRAM MODULE
1K x 32 bits
(2 Kwords)
LESS SIGNIFICANT WORD
LEAST SIGNIFICANT WORD
MORE SIGNIFICANT WORD
MOST SIGNIFICANT WORD
SINGLE WORD
SINGLE WORD
0
3
1
5
2
SINGLE WORD
7
4
6
LESS SIGNIFICANT WORD
LEAST SIGNIFICANT WORD
SINGLE WORD
ADDRESS
ADDRESS
ALIGNED DOUBLE WORD AND DOUBLE-WORD ADDRESS
MISALIGNED DOUBLE WORD AND DOUBLE-WORD ADDRESS
KEY:
16 bits
32 bits
EVEN BANK
ODD BANK
MOST SIGNIFICANT WORD