Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Systems Inc.
50
8 Timing Characteristics and Requirements
(continued)
8.11 SIU
(continued)
Note:
It is assumed that the SIU is configured with OCKA(
SCON10
[6]) = 1 for active mode output clock, OCKK(
SCON10
[7]) = 0 for no inver-
sion of SOCK, OFSA(
SCON10
[4]) = 1 for active mode output frame sync, OFSK(
SCON10
[5]) = 0 for no inversion of SOFS,
OMSB(
SCON0
[10]) = 0 for LSB-first output, OFRAME(
SCON2
[7]) = 1 for frame mode output, and OFSDLY[1:0](
SCON2
[9:8]) = 00 for
no output frame sync delay.
Figure 32. SIU Active Channel Mode Output Timing Diagram
Table 55. Timing Requirements for SIU Active Channel Mode Output
Abbreviated
Reference
t51
Parameter
Min
Max
Unit
SOCK Bit Clock Period (high to high)
61.035
The active clock source is programmed as either the internal clock CLK or the SCK pin, depending on the AGEXT field (
SCON12
[12]). The
period of SOCK is dependent on the period of the active clock source and the programming of the AGCKLIM[7:0] field (
SCON11
[7:0]). The
application must ensure that the period of SOCK is at least 61.035 ns.
—
ns
Table 56. Timing Characteristics for SIU Active Channel Mode Output
Abbreviated
Reference
t52
t53
t54
t55
t56
t57
Parameter
Min
Max
Unit
SOCK Bit Clock High Time (high to low)
SOCK Bit Clock Low Time (low to high)
SOFS Delay (high to high)
SOD Data Delay (high to valid)
SOD Data Hold (high to invalid)
SOD Deactivation Delay (high to 3-state)
T
AGCKH
–
3
T
AGCKL
–
3
T
CKAG
–
5
0
–
3
—
T
AGCKH
and T
AGCKL
are dependent on the programming of the AGCKLIM[7:0] field (
SCON11
[7:0]) and the period of the active clock source.
T
CKAG
is the period of the active clock source. The active clock source is programmed as either the internal clock CLK or the SCK pin,
depending on the AGEXT field (
SCON12
[12]).
T
AGCKH
+ 3
T
AGCKL
+ 3
T
CKAG
+ 5
16
5
15
ns
ns
ns
ns
ns
5-8028 (F)
t51
t52
t53
t55
SOCK
SOFS
SOD
B0
B1
t56
B0
t54
t57