
Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
293
11 Timing Characteristics and Requirements
(continued)
11.10 PIU
(continued)
PSTRN is the logical OR of the PCSN input pin with the exclusive NOR of the PIDS and PODS input pins, i.e.,
PSTRN = PCSN | (PIDS ^ PODS).
It is assumed that the PRDYMD pin is logic low, configuring the PRDY pin as active-low.
Figure 83. Host Data Read from PDO Timing Diagram
Table 207. Timing Requirements for PIU Data Read Operations
Abbreviated Reference
t60
t61
t62
t65
t74
Parameter
Min
Max
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
PSTRN Pulse Width (high to low or low to high)
PADD Setup Time
(valid to low)
PADD Hold Time
(low to invalid)
PSTRN Request Period (low to low)
PSTRN Hold (low to high)
max (2T
, 15)
5
5
max (5T
, 30)
1
T is the period of the internal clock (CLK).
Time to the falling edge of PIDS, PODS, or PCSN, whichever occurs last.
Table 208. Timing Characteristics for PIU Data Read Operations
Abbreviated Reference
t69
t70
t71
t72
t73
Parameter
Min
1
T – 3
1
1
1
Max
12
T
6
12
12
Unit
ns
ns
ns
ns
ns
PRDY Delay (low to valid)
POBE, PRDY Delays (valid to low)
PD Activation Delay
(low to low-Z)
POBE Delay
(high to high)
PD Deactivation Delay
(high to 3-state)
Delay from the falling edge of PIDS, PODS, or PCSN, whichever occurs last.
Delay from the rising edge of PIDS, PODS, or PCSN, whichever occurs first.
PSTRN
PADD[3:0]
PD[15:0]
POBE
PRDY
t65
t60
t60
t61
t62
t73
t71
t72
t70
t74
t69