
Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
77
4 Hardware Architecture
(continued)
4.13 Direct Memory Access Unit (DMAU)
(continued)
4.13.2 Registers
(continued)
Table 38. SCNT
0—3
(SWT
0—3
Source Counter) Registers
See
Table 29 starting on page 66
for the memory addresses of these registers.
19—7
SROW[12:0]
Table 39. SCNT
4—5
(MMT
4—5
Source Counter) Registers
See
Table 29 starting on page 66
for the memory addresses of these registers.
19—7
SROW[12:0]
6—0
SCOL[6:0]
Bit
Field
Description
R/W
Reset
Value
X
19—7
SROW[12:0]
The row counter of the one-dimensional or two-dimensional source array for
the corresponding SWT channel (read data). The DMAU updates this field
as the transfer proceeds and automatically clears it upon the completion of
the transfer.
The column counter of the one-dimensional or two-dimensional source array
for the corresponding SWT channel (read data). The DMAU updates this
field as the transfer proceeds and automatically clears it upon the completion
of the transfer.
For this column, X indicates unknown on powerup reset and unaffected on subsequent reset.
SCNT
0—3
are not cleared by a reset of the DMAU
channel via the
DMCON1
register (
Table 32 on page 71
). Before an SWT channel can be used, the program must clear the corresponding
SCNT
0—3
register after a DSP16410B device reset. Otherwise, the value of this register is undefined.
R/W
6—0
SCOL[6:0]
R/W
X
6—0
SCOL[6:0]
Bit
Field
Description
R/W
Reset
Value
X
19—7
SROW[12:0]
The row counter of the source block for the corresponding MMT channel
(read data). The DMAU increments this field as the transfer proceeds and
automatically clears it upon the completion of the transfer.
The column counter of the source block for the corresponding MMT channel
(read data). Typically, the user has programmed the LASTCOL[6:0] field
(
LIM
4—5
[6:0]—
Table 43 on page 79
) with zero, and therefore, the DMAU
does not update this field.
For this column, X indicates unknown on powerup reset and unaffected on subsequent reset.
SCNT
4—5
are not cleared by a reset of the DMAU
channel via the
DMCON1
register (
Table 32 on page 71
). Before an MMT channel can be used, the program must clear the corresponding
SCNT
4—5
register after a DSP16410B device reset. Otherwise, the value of this register is undefined.
R/W
6—0
SCOL[6:0]
R/W
X