Data Sheet
June 2001
DSP16410B Digital Signal Processor
300
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
11 Timing Characteristics and Requirements
(continued)
11.11 SIU
(continued)
Note:
It is assumed that the SIU is configured with ICKA(
SCON10
[2]) = 1 for active mode input clock, ICKK(
SCON10
[3]) = 0 for no inversion of
SICK, IFSA(
SCON10
[0]) = 1 for active mode input frame sync, IFSK(
SCON10
[1]) = 0 for no inversion of SIFS, IMSB(
SCON0
[2]) = 0 for
LSB-first input, and IFSDLY[1:0](
SCON1
[9:8]) = 00 for no input frame sync delay.
Figure 90. SIU Active Frame and Channel Mode Input Timing Diagram
Table 220. Timing Requirements for SIU Active Frame Mode Input
Abbreviated Reference
t45
t49
t50
Parameter
Min
25
9
8
Max
—
—
—
Unit
ns
ns
ns
SICK Bit Clock Period (high to high)
SID Setup Time (valid to low)
SID Hold Time (low to invalid)
The active clock source is programmed as either the internal clock CLK or the SCK pin, depending on the AGEXT field (
SCON12
[12]). The
period of SICK is dependent on the period of the active clock source and the programming of the AGCKLIM[7:0] field (
SCON11
[7:0]). The
application must ensure that the period of SICK is at least 25 ns.
Table 221. Timing Characteristics for SIU Active Frame Mode Input
Abbreviated Reference
t46
t47
t48
Parameter
Min
Max
Unit
ns
ns
ns
SICK Bit Clock High Time (high to low)
SICK Bit Clock Low Time (low to high)
SIFS Delay (high to high)
T
AGCKH
– 3
T
AGCKL
– 3
T
CKAG
– 5
T
AGCKH
and T
AGCKL
are dependent on the programming of the AGCKLIM[7:0] field (
SCON11
[7:0]) and the period of the active clock source.
T
CKAG
is the period of the active clock source. The active clock source is programmed as either the internal clock CLK or the SCK pin, depend-
ing on the AGEXT field (
SCON12
[12]).
T
AGCKH
+ 3
T
AGCKL
+ 3
T
CKAG
+ 5
5-8029 (F)
t45
t46
t47
t48
SICK
SIFS
SID
B0
B1
B2
t49
t50
B0