
Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
239
6 Software Architecture
(continued)
6.2 Registers
(continued)
6.2.3 Register Encodings
(continued)
Table 150. ins (Interrupt Status) Register
Table 151. mgi (Core-to-Core Message Input) Register
Table 152. mgo (Core-to-Core Message Output) Register
Table 153. pid (Processor Identification) Register
19
18
17
16
15
14
13
12
XIO
2
MXI0
11
10
MXI9
9
INT1
MXI8
8
INT0
MXI7
7
DMINT5
MXI6
6
DMINT4
MXI5
5
MXI3
MXI4
4
MXI2
PHINT
3
MXI1
SIGINT
1
TIME1
MGIBF
0
TIME0
Field
Value
Description
R/W
Reset
Value
0
MXI
0—9
PHINT
XIO
SIGINT
MGIBF
INT
0—1
DMINT
4—5
TIME
0—1
See
Table 5 on page 28
for definition of MXI
0—9
(IMUX
0—9
).
0
Read—corresponding interrupt not pending.
Write—no effect.
R/Clear
1
Read—corresponding interrupt is pending.
Write—clears bit and changes corresponding interrupt status to not
pending.
15—0
Message Input
Bit
15—0
Field
Description
R/W Reset Value
R
Message Input
Full-duplex message buffer that holds the input data word.
0
15—0
Message Output
Bit
15—0
Field
Description
R/W Reset Value
W
Message Output
Full-duplex message buffer that holds the output data word.
0
15—0
PID
Bit
15—0
Field
PID
Value
Description
R/W
R
Reset Value
0x0000
0x0001
0x0000
0x0001
CORE0
CORE1
Processor identification to allow the software to distin-
guish whether it is running on CORE0 or CORE1.
CORE0
CORE1