Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
63
4 Hardware Architecture
(continued)
4.13 Direct Memory Access Unit (DMAU)
The DMAU (direct memory access unit) manages
movement of data to or from the DSP16410B internal
or external memory with minimal core intervention:
The DMAU can move data between memory and the
I/O units:
—The DMAU provides four single-word transfer
(SWT) channels for moving data between memory
and SIU
0—1
. A core initially defines the data
structure and the DMAU provides address genera-
tion, compare, and update functions. Two-dimen-
sional array capability facilitates applications such
as TDM channel multiplexing/demultiplexing.
Each SWT channel allows an SIU to access mem-
ory one word (16 bits) at a time.
—The DMAU provides a single addressing bypass
channel for moving data between memory and the
PIU. Unlike the SWT channels, the bypass chan-
nel does not provide address generation, com-
pare, and update functions. The bypass channel
allows a host to address and access memory one
word (16 bits) at a time.
The DMAU can move data between two blocks of
memory. It provides two memory-to-memory (MMT)
channels for which a core initially defines the data
structure. The DMAU provides address generation,
compare, and update functions for each channel.
The DMAU can perform a block transfer either a sin-
gle word (16 bits) at a time or a double word (32 bits)
at a time.
4.13.1 Overview
The DMAU has six independent channels and an
addressing bypass channel as detailed in
Table 28
.
These channels can access any DSP16410B memory
component, including TPRAM0, TPRAM1, and external
memory.
Figure 18 on page 64
is a functional overview of the
DMAU channels and their interconnections to the
peripherals and memory buses. The DMAU arbitrates
among the seven channels for access to the memory.
For an SWT channel, a core can define a data struc-
ture (array) in DSP16410B memory by programming
DMAU memory-mapped registers. The DMAU can
then perform source or destination
transfers
. A
source
transfer
is defined as a series of read operations from
the memory array to an SIU. A
destination transfer
is
defined as a series of write operations to the memory
array from an SIU. A transfer consists of a series of
transactions
in response to SIU requests. A
source
transaction
is defined as reading a word (16 bits) from
the array, writing the word to the SIU output data regis-
ter (
SODR
), and updating the appropriate DMAU
registers. A
destination transaction
is defined as
reading a word from the SIU input data register (
SIDR
),
writing the word to the array, and updating the appropri-
ate DMAU registers. See
Section 4.13.5
for details on
SWT transactions.
The DMAU also provides two channels for memory-to-
memory transfers (MMT). These channels allow a
user-defined block of data to be transferred between
any two DSP16410B memory blocks, including exter-
nal memory. Each MMT channel transfers data
between a
source block
and a
destination
block
. The DMAU can perform a block transfer either a
single word (16 bits) at a time or a double word
(32 bits) at a time. See
Section 4.13.6
for details on
memory-to-memory block transfers.
Finally, the DMAU provides an addressing bypass
channel that is dedicated to the PIU. This channel
bypasses the DMAU address generation, compare,
and update processes. The DMAU relies on the PIU to
provide the memory address for each PIU transaction
Table 28. DMAU Channel Assignment
DMAU Channel
SWT0
SWT1
SWT2
SWT3
MMT4
MMT5
Bypass
Description
Associated With
SIU0
Single-word (16-bit) transfers
Single-word (16-bit) transfers
Single-word (16-bit) transfers
Single-word (16-bit) transfers
Single-word (16-bit) or double-word (32-bit) transfers
Single-word (16-bit) or double-word (32-bit) transfers
Single-word (16-bit) transfers
SIU1
Memory
PIU