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參數(shù)資料
| 型號(hào)： | DSP16410C |
| 英文描述： | TVS 400W 7.0V UNIDIRECT SMA |
| 中文描述： | DSP1629數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 73/373頁(yè) |
| 文件大?。?/td> | 5643K |
| 代理商： | DSP16410C |
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Table 1. DSP16410B Block Diagram Legend
(continued)
Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
17
4 Hardware Architecture
(continued)
4.1 DSP16410B Architectural Overview
(continued)
4.1.1 DSP16000 Cores
The two DSP16000 cores (CORE0 and CORE1) are
the signal processing engines of the DSP16410B. The
DSP16000 is a modified Harvard architecture with sep-
arate sets of buses for the instruction/coefficient
(X-memory) and data (Y-memory) spaces. Each set of
buses has 20 bits of address and 32 bits of data. The
core contains data and address arithmetic units and
control for on-chip memory and peripherals.
4.1.2 Clock Synthesizer (PLL)
The DSP16410B powers up with an input clock (CKI)
as the source for the processor clock (CLK). An on-
chip clock synthesizer (PLL) that runs at a frequency
multiple of CKI can also be used to generate CLK. The
clock synthesizer is deselected and powered down on
reset. The selection of the clock source is under soft-
ware control of CORE0. See
Section 4.17 beginning
on page 197
for details.
4.1.3 Triport RAMs (TPRAM
0—1
)
Each core has a private block of TPRAM consisting of
96 banks (banks 0—95) of zero wait-state memory.
Each bank consists of 1K 16-bit words and has three
separate address and data ports: one port to the core’s
instruction/coefficient (X-memory) space, a second
port to the core’s data (Y-memory) space, and a third
port to the DMA (Z-memory) space. TPRAM0 is
accessible by CORE0, TPRAM1 is accessible by
CORE1, and both TPRAM0 and TPRAM1 are accessi-
ble by the DMAU. TPRAM is organized into even and
odd interleaved banks for which each even/odd
address pair is a 32-bit wide module (see
Section 4.6
on page 43
for details). The TPRAMs support single-
word, aligned double-word, and misaligned double-
word accesses.
4.1.4 Shared Local Memory (SLM)
The SLM consists of two banks of memory. Each bank
consists of 1K 16-bit words. The SLM can be
accessed by both cores and by the DMAU and PIU
over the system bus (SAB, SDB). The SLM supports
single-word (16-bit) and aligned double-word (32-bit)
accesses. Misaligned double-word accesses are not
supported. An access to the SLM takes multiple clock
cycles to complete, and a core access to the SLM
causes the core to incur wait-states. See
Section 4.14.7.1 on page 125
for details on system bus
performance.
4.1.5 Internal Boot ROMs (IROM
0—1
)
Each core has its own boot ROM that contains a single
boot routine and software to support the Agere hard-
ware development system (HDS). The code in IROM0
and IROM1 are identical. See
Section 5 on page 205
for details.
4.1.6 Messaging Units (MGU
0—1
)
The DSP16410B provides an MGU for each core:
MGU0 for CORE0 and MGU1 for CORE1. The MGUs
provide interprocessor (core-to-core) communication
and interrupt generation. See
Section 4.8 on page 45
for details.
TPRAM
0—1
96 Kword Three-Port Random-Access Memories (one for each core). Private code (X), data (Y), and
DMA (Z).
20-Bit X-Memory Space Address Bus. One for each core.
32-Bit X-Memory Space Data Bus. One for each core.
20-Bit Y-Memory Space Address Bus. One for each core.
32-Bit Y-Memory Space Data Bus. One for each core.
20-Bit External Z-Memory Space Address Bus. Interfaces DMAU to SEMI.
32-Bit External Z-Memory Space Data Bus. Interfaces DMAU to SEMI.
20-Bit Internal Z-Memory Space Address Bus. Interfaces DMAU to TPRAM0 and TPRAM1.
32-Bit Internal Z-Memory Space Data Bus. Interfaces DMAU to TPRAM0 and TPRAM1.
External Segment Address Bits Associated with ZEAB. Interfaces DMAU to SEMI.
XAB
0—1
XDB
0—1
YAB
0—1
YDB
0—1
ZEAB
ZEDB
ZIAB
ZIDB
ZSEG
Symbol
Description
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