Data Sheet
June 2001
DSP16410B Digital Signal Processor
166
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
4 Hardware Architecture
(continued)
4.16 Serial Interface Unit (SIU)
(continued)
4.16.8 Basic Frame Structure
(continued)
Figure 48. Basic Frame Structure with Idle Time
To assist channel selection within a frame, a frame is
partitioned into a maximum of eight subframes. Each
subframe has 16 logical channels, for a total channel
capacity of 128 channels per frame.
4.16.9 Assigning SIU Logical Channels to DMAU
Channels
Regardless of the operating mode, the channel index
registers for the SIU must be initialized via software if
the DMAU is used to transfer data to and from memory.
There are a total of four 16-bit channel index registers:
two for input (
ICIX
0—1
) and two for output
(
OCIX
0—1
). Each bit corresponds to one logical
channel within the currently selected even or odd sub-
frame. These bit fields determine the assignment of
logical channels within a subframe to a specific DMAU
SWT channel dedicated to that SIU. Recall that two
bidirectional SWT channels of the DMAU support each
SIU so that logical channels can be routed to two sepa-
rate memory spaces.
In channel mode,
ICIX0
corresponds to the currently
selected even input subframe, as determined by the
ISFID_E[1:0] field (
SCON3
[1:0]—see
Table 104 on
page 185
).
ICIX1
corresponds to the currently
selected odd input subframe, as determined by the
ISFID_O[1:0] field (
SCON3
[4:3]).
OCIX0
corresponds
to the currently selected even output subframe, as
determined by the OSFID_E[1:0] field
(
SCON3
[9:8]—see
Table 104 on page 185
).
OCIX1
corresponds to the currently selected odd output sub-
frame, as determined by the OSFID_O[1:0] field
(
SCON3
[12:11]). In frame mode,
ICIX
0—1
and
OCIX
0—1
are circularly mapped to multiple channels
in the frame as illustrated by
Table 120 on page 196
and
Table 119 on page 195
.
If a bit field of SIU0’s
ICIX
0—1
or
OCIX
0—1
regis-
ter is cleared, the corresponding logical channel of
SIU0 is assigned to SWT0. If a bit field of these regis-
ters is set to one, the corresponding logical channel of
SIU0 is assigned to SWT1. If a bit field of SIU1’s
ICIX
0—1
or
OCIX
0—1
register is cleared, the cor-
responding logical channel of SIU1 is assigned to
SWT2. If a bit field of these same registers is set to
one, the corresponding logical channel of SIU1 is
assigned to SWT3. For example, to assign SIU0 input
channels 0 to 7 to SWT0 and 8 to 15 to SWT1, the
value written to
ICIX0
is 0xFF00.
CHANNEL
I,O
SIZE
FRAME PERIOD
I,O
FLIM + 1 CHANNELS
I,O
CK
S
I,O
D
I,O
FS
0
2
1
7
6
5
3 4
0
2
1
7
6
5
3 4
0
2
1
7
6
5
3 4
0
2
1
7
6
5
3 4
0
2
1
7
6
5
3 4
0
2
1
5
3 4
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 0
FRAME
0
0
0
0
0 0
IDLE
The SIU 3-states SOD during idle time.