Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
243
6 Software Architecture
(continued)
6.2 Registers
(continued)
6.2.3 Register Encodings
(continued)
Table 159. sbit (BIO Status/Control) Register
\
Table 160. signal (Core-to-Core Signal) Register
15
14—8
7
6—0
Reserved
DIREC[6:0]
Reserved
VALUE[6:0]
Bit
Field
Value
Description
R/W
Reset
Value
0
0
For this column, X indicates unknown on powerup reset and unaffected on subsequent reset.
This field is read-only—writing the VALUE[6:0] field of
sbit
has no effect. If the user software toggles a bit in the DIREC[6:0] field, there is a latency of
one cycle until the VALUE[6:0] field reflects the current state of the corresponding IO
0,1
BIT[6:0] pin. If an IO
0,1
BIT[6:0] pin is configured as an out-
put (DIREC[6:0] = 1) and the user software writes
cbit
to change the state of the pin, there is a latency of two cycles until the VALUE[6:0] field reflects
the current state of the corresponding IO
0,1
BIT[6:0] output pin.
§ The IO
0,1
BIT[6:0] pins are configured as inputs after reset. If external circuitry does not drive an IO
0,1
BIT[n] pin, the VALUE[n] field is undefined
after reset.
15
Reserved
DIREC[6:0]
(Controls direc-
tion of pins)
Reserved
VALUE[6:0]
(Current value of
pins)
0
0
1
Reserved—write with zero.
Configure the corresponding IO
0,1
BIT[6:0] pin as an input.
Configure the corresponding IO
0,1
BIT[6:0] pin as an output.
R/W
R/W
14—8
7
—
0
1
Reserved.
The current state of the corresponding IO
0,1
BIT[6:0] pin is logic 0.
The current state of the corresponding IO
0,1
BIT[6:0] pin is logic 1.
R
R
X
P
§
6—0
15—11
Reserved
1
0
SIGTRAP
SIGINT
Bit
Field
Value
Description
R/W
Reset
Value
0
0
15—11
1
Reserved
SIGTRAP
0
0
1
0
1
Reserved—write with zero.
No effect.
Trap the other core by asserting its PTRAP signal.
No effect.
Interrupt the other core by asserting its SIGINT interrupt.
W
W
0
SIGINT
W
0
Note: If the program sets the SIGTRAP or SIGINT field, the MGU automatically clears the field after asserting the trap or interrupt. Therefore, the pro-
gram must not explicitly clear the field.