Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
105
4 Hardware Architecture
(continued)
4.14 System and External Memory Interface
(SEMI)
(continued)
4.14.1 External Interface
(continued)
4.14.1.4 Address and Data
The SEMI provides a 32-bit external data bus,
ED[31:0]. If the external memory is configured for
16-bit data (the ESIZE input pin is low), the SEMI uses
only the upper half of the data bus (ED[31:16]). The
SEMI provides a 19-bit external address bus, EA[18:0],
to select a location within the selected external mem-
ory component (ERAM, EIO, or EROM). If the external
memory is configured for 16-bit data, the SEMI uses
EA[18:0] to address single (16-bit) words within the
selected memory component. If the external memory
is configured for 32-bit data (the ESIZE input pin is
high), the SEMI uses EA[18:1] to address double
(32-bit) words within the selected memory component
and does not use EA0 as an address bit. For more
detail, see
Table 55
or
Section 4.14.2
.
The SEMI provides the ESEG[3:0] pins to expand the
size of each of the external memory components using
one of the following methods:
1. ESEG[3:0] can be interpreted by the external mem-
ory system as four separate decoded address
enable signals. Each ESEG[3:0] pin individually
selects one of four segments for each memory
component. This results in four glueless 512 Kword
(1 Mbyte) ERAM segments, four glueless 512 Kword
(1 Mbyte) EROM segments, and four glueless
128 Kword (256 Kbytes) EIO segments.
2. ESEG[3:0] can be interpreted by the external mem-
ory system as an extension of the address bus, i.e.,
the ESEG[3:0] pins can be concatenated with the
EAB[18:0] pins to form a 23-bit address. This results
in one glueless 8 Mword (16 Mbytes) ERAM seg-
ment, one glueless 8 Mword (16 Mbytes) EROM
segment, and one glueless 2 Mword (4 Mbytes) EIO
segment.
For external accesses by either core, the SEMI places
the contents of a field in one of four segment address
extension registers onto the ESEG[3:0] pins. The four
segment address extension registers are described in
Section 4.14.4
. For external accesses by the DMAU or
PIU, the contents of address registers within those
units determine the state of the ESEG[3:0] pins. See
Table 55
for more detail.
Table 55. Address and Data Bus Pins for the SEMI External Interface
Pins
Description
ED[31:16]
(input/output)
If the external memory is configured for 16-bit data (the ESIZE pin is low), the SEMI uses ED[31:16] for all
external accesses.
If the external memory is configured for 32-bit data (the ESIZE pin is high), the SEMI uses ED[31:16] if:
— The SEMI is accessing a single word (16 bits) at an even address.
— The SEMI is accessing a double word at an even (aligned) address.
— The SEMI is accessing the least significant half of a double word at an odd (misaligned) double-word
address.
If the SEMI is not currently performing one of the above types of accesses, it 3-states ED[31:16].
If the external memory is configured for 32-bit data (the ESIZE pin is high), the SEMI uses ED[15:0] if:
— The SEMI is accessing a single word (16 bits) at an odd address.
— The SEMI is accessing a double word at an even (aligned) address.
— The SEMI is accessing the most significant half of a double word at an odd (misaligned) double-word
address.
ED[15:0]
(input/output)
If the SEMI is not currently performing one of the above types of accesses, it 3-states ED[15:0].
The EROM component is synchronous if the ERTYPE pin is logic 1. The ERAM component is synchronous if YTYPE field (
ECON1
[9]) is set. The EIO
component is synchronous if the ITYPE field (
ECON1
[10]) is set.
ECON1
is described in
Table 60 on page 110
.