Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
69
4 Hardware Architecture
(continued)
4.13 Direct Memory Access Unit (DMAU)
(continued)
Table 30. DSTAT (DMAU Status) Register
(continued)
4.13.2 Registers
(continued)
17
SRDY3
1
0
1
0
1
SWT3 has a source transaction pending.
SWT3 does not have a source transaction pending.
SWT3 has a destination transaction pending.
SWT3 does not have a destination transaction pending.
SWT3 has detected a protocol error (source or destination). Error report is cleared by
writing a 1 to this bit.
SWT3—no errors.
SWT2 is reading memory.
SWT2 is not reading memory.
SWT2 is writing memory.
SWT2 is not writing memory.
SWT2 has a source transaction pending.
SWT2 does not have a source transaction pending.
SWT2 has a destination transaction pending.
SWT2 does not have a destination transaction pending.
SWT2 has detected a protocol error (source or destination). Error report is cleared by
writing a 1 to this bit.
SWT2—no errors.
SWT1 is reading memory.
SWT1 is not reading memory.
SWT1 is writing memory.
SWT1 is not writing memory.
SWT1 has a source transaction pending.
SWT1 does not have a source transaction pending.
SWT1 has a destination transaction pending.
SWT1 does not have a destination transaction pending.
SWT1 has detected a protocol error (source or destination). Error report is cleared by
writing a 1 to this bit.
SWT1—no errors.
SWT0 is reading memory.
SWT0 is not reading memory.
SWT0 is writing memory.
SWT0 is not writing memory.
SWT0 has a source transaction pending.
SWT0 does not have a source transaction pending.
SWT0 has a destination transaction pending.
SWT0 does not have a destination transaction pending.
SWT0 has detected a protocol error (source or destination). Error report is cleared by
writing a 1 to this bit.
SWT0—no errors.
R
X
16
DRDY3
R
X
15
ERR3
R/Clear
X
0
1
0
1
0
1
0
1
0
1
14
SBSY2
R
X
13
DBSY2
R
X
12
SRDY2
R
X
11
DRDY2
R
X
10
ERR2
R/Clear
X
0
1
0
1
0
1
0
1
0
1
9
SBSY1
R
X
8
DBSY1
R
X
7
SRDY1
R
X
6
DRDY1
R
X
5
ERR1
R/Clear
X
0
1
0
1
0
1
0
1
0
1
4
SBSY0
R
X
3
DBSY0
R
X
2
SRDY0
R
X
1
DRDY0
R
X
0
ERR0
R/Clear
X
0
Bits
Field
Value
Description
R/W
Reset
Value
For this column, X indicates unknown on powerup reset and unaffected on subsequent reset.
A core resets MMT5 by setting the RESET5 field (
DMCON1
[5]—
Table 32 on page 71
) and resets MMT4 by setting the RESET4 field (
DMCON1
[4]).