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參數(shù)資料
| 型號(hào)： | DSP16410C |
| 英文描述： | TVS 400W 7.0V UNIDIRECT SMA |
| 中文描述： | DSP1629數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 258/373頁(yè) |
| 文件大小： | 5643K |
| 代理商： | DSP16410C |
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Data Sheet
June 2001
DSP16410B Digital Signal Processor
202
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
4 Hardware Architecture
(continued)
4.20 Power Management
A program running in a core can place that core into
low-power standby mode by setting the AWAIT field
(
alf
[15]—see
Table 140 on page 232
). In this mode,
the clock to that core and its associated TPRAM are
disabled except for the minimum core circuitry required
to process an incoming interrupt or trap. The clock to
the peripherals is unaffected.
Figure 56 on page 203
illustrates the following:
Distribution of CLK to the cores and peripherals.
Function of the AWAIT field.
Interrupts to the core used to exit low-power standby
mode.
ECKO pin selection logic (see
Section 4.19 on page
201
for details).
If a core is in low-power standby mode, program exe-
cution in that core is suspended without loss of state. If
an interrupt that was enabled by that core occurs or if a
trap occurs, the core clears its AWAIT field, exits low-
power standby mode, resumes program execution, and
services the interrupt or trap. See
Section 4.4.5 on
page 30
and
Section 4.4.6 on page 31
for information
on enabling interrupts.
If the DMAU accesses the TPRAM while the associ-
ated core is in standby mode, the clock to the TPRAM
is re-enabled for that access. However, if the core
goes into standby mode while an access to a memory
component is in progress, it locks out the DMAU from
accessing that component. To prevent locking out the
DMAU, the user program must use the macro
SLEEP_ALF ()
in the
16410.h
file. The
16410.h
file is
included with the Agere software generation system
(SGS) tools. Using
SLEEP_ALF ()
guarantees that the
core completes all pending memory accesses before
entering standby mode.
SLEEP_ALF ()
expands to the following:
.align
goto .+1
alf=0x8000
3*nop
If CORE0 is entering low-power standby mode, it can
further save power by doing one or more of the follow-
ing prior to entering standby mode:
1. Select the CKI pin as the source clock to the cores
and peripherals by clearing the PLLSEL field
(
pllcon
[0]—see
Table 122 on page 199
).
2. Disable (power down) the PLL by clearing the
PLLEN field (
pllcon
[1]).
3. Drive the ECKO
1
pin low by programming the
ECKO[1:0] field (
ECON1
[1:0]—see
Table 60 on
page 110
) to 3.
Options 1 and 2 result in increased wake-up latency,
which is the delay from the time that the core exits
standby mode (due to an interrupt) to the time that the
core resumes full-speed execution. Before selecting
these options, the programmer must ensure that the
increased wake-up latency is acceptable in the applica-
tion.
Table 125
compares the wake-up latency for vari-
ous selections of clocks during standby mode. It also
illustrates the trade-off of wake-up latency vs. power
consumption. Disabling the PLL during low-power
standby mode results in the minimum power consump-
tion and highest wake-up latency. See
Section 10.3 on
page 271
and
Section 11.2 on page 278
for details on
power dissipation and wake-up latency for various
operating modes.
Table 125. Wake-Up Latency and Power Consumption for Low-Power Standby Mode
Source Clock
Selected In Standby
Mode
PLL
Enabled
CKI Pin
Enabled
Disabled
1. Although
ECON1
can be accessed by either core, the programmer should select only one core (such as CORE0) to control the ECKO
pin. The programmer is responsible for developing a protocol between CORE0 and CORE1. Intercore coordination is not part of the
DSP16410B hardware.
Status of PLL In
Standby Mode
Wake-Up Latency
Latency vs. Power Consumption Trade-off
3 PLL cycles
3 CKI cycles
3 CKI cycles +
PLL lock-in time
Minimum wake-up latency (highest power)
—
Minimum power (highest wake-up latency)
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