Data Sheet
June 2001
DSP16410B Digital Signal Processor
94
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
4 Hardware Architecture
(continued)
4.13 Direct Memory Access Unit (DMAU)
(continued)
4.13.9 Programming Examples
This section illustrates three typical DMAU applications.
4.13.9.1 SWT Example 1: A Two-Dimensional Array
This example describes the input and output of four channels of full-duplex TDM speech data from SIU0 with the
following assumptions:
The data is double-buffered to avoid latencies and the potential of missing samples.
Input and output data have the same array size and structure and are processed by the SWT0 channel.
There are four ogical channels (time slots) grouped in four contiguous double buffers, corresponding to the num-
ber of columns (n) in a two-dimensional array.
Each single buffer has 160 elements, or rows (r), and each double buffer has a length of 320 (0x140).
CORE0 begins processing data after 160 samples have been input for all four logical channels.
SIU0 input (destination) data begins at address 0x01000 in TPRAM0.
SIU0 output (source) data begins at address 0x02000 in TPRAM0.
The autoload feature is used to minimize core intervention.
Figure 23
illustrates this data structure. This example does not discuss the setup and control of SIU0.
A Two-Dimensional Data Structure for Double-Buffering n Channels
Figure 23. Example of a Two-Dimensional Double-Buffered Data Structure
S
(SBAS0)
SOURCE
ARRAY
COMPLETE
DESTINATION
ARRAY COMPLETE
(SIGCON=0x5)
OUTPUT SOURCE ARRAY
INPUT DESTINATION ARRAY
SOURCE
BUFFER
COMPLETE
DESTINATION
BUFFER COMPLETE
(SIGCON=0x3)
0x02000
0x02140
0x02280
0x023C0
ROW=0
ROW=1
ROW=319
ROW=0
ROW=1
ROW=159
C
S
B
D
B
ROW=319
ROW=0
ROW=1
ROW=159
ROW=319
ROW=0
ROW=1
ROW=159
ROW=319
ROW=159
C
C
C
(DBAS0)
0x01000
0x01140
0x01280
0x013C0
ROW=0
ROW=1
ROW=319
ROW=0
ROW=1
ROW=159
C
S
B
D
B
ROW=319
ROW=0
ROW=1
ROW=159
ROW=319
ROW=0
ROW=1
ROW=159
ROW=319
ROW=159
C
C
C
R
A
R
A
(
S
(