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參數(shù)資料
| 型號(hào)： | DSP16410C |
| 英文描述： | TVS 400W 7.0V UNIDIRECT SMA |
| 中文描述： | DSP1629數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 159/373頁(yè) |
| 文件大小： | 5643K |
| 代理商： | DSP16410C |
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Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
103
4 Hardware Architecture
(continued)
4.14 System and External Memory Interface (SEMI)
(continued)
4.14.1 External Interface
(continued)
4.14.1.3 Enables and Strobes
The SEMI provides a negative-assertion external memory enable output pin for each of the three external memory
components, ERAM, EIO, and EROM. These pins are the active-low enables for the external memory components
ERAM (external RAM), EROM (external ROM), and EIO (external I/O). Refer to the memory maps described in
Section 4.5 on page 37
and shown in Figures
6
,
7
,
8
, and
9
for details about these memory components. The
SEMI provides two negative-assertion write strobe output pins, ERWN[1:0].
Table 54
details the SEMI enables and
strobe pins. The SEMI 3-states the enables and strobes if it grants a request by an external device to access the
external memory (see description of the EREQN pin in
Table 53 on page 102
).
Table 54. Enable and Strobe Pins for the SEMI External Interface
Pin
Value
0
Description
ERAMN
(negative-
assertion output)
The SEMI is selecting the ERAM memory component for an access. The SEMI asserts this enable
for a duration based on whether the ERAM memory component is configured as asynchronous or
synchronous:
If the ERAM memory component is configured as asynchronous (the YTYPE field
(
ECON1
[9]—see
Table 60 on page 110
) is cleared), the SEMI asserts ERAMN for the number of
instruction cycles specified by the YATIME[3:0] field (
ECON0
[7:4]—see
Table 59 on page 109
).
If the ERAM memory component is configured as synchronous (the YTYPE field is set), the SEMI
asserts ERAMN for two instruction cycles (one ECKO cycle
) for a read or write operation.
The SEMI is not selecting the ERAM memory component for an access.
The SEMI 3-states ERAMN if it grants a request by an external device to access the external mem-
ory (see description of the EREQN pin in
Table 53 on page 102
).
The SEMI is selecting the EIO memory component for an access. The SEMI asserts this enable for
a duration based on whether the EIO memory component is configured as asynchronous or syn-
chronous:
1
Z
EION
(negative-
assertion output)
0
If the EIO memory component is configured as asynchronous (the ITYPE field (
ECON1
[10]—see
Table 60 on page 110
) is cleared), the SEMI asserts EION for the number of instruction cycles
specified by the IATIME[3:0] field (
ECON0
[11:8]—see
Table 59 on page 109
).
If the EIO memory component is configured as synchronous (the ITYPE field is set), the SEMI
asserts EION for two instruction cycles (one ECKO cycle
) for a read or write operation.
The SEMI is not selecting the EIO memory component for an access.
The SEMI 3-states EION if it grants a request by an external device to access the external memory
(see description of the EREQN pin in
Table 53 on page 102
).
The SEMI is selecting the EROM memory component for an access
. The SEMI asserts this enable
for a duration based on whether the EROM memory component is configured as asynchronous or
synchronous:
1
Z
EROMN
(negative-
assertion output)
0
If the EROM memory component is configured as asynchronous (the ERTYPE pin is low), the
SEMI asserts EROMN for the number of instruction cycles specified by the XATIME[3:0] field
(
ECON0
[3:0]—see
Table 59 on page 109
).
If the EROM memory component is configured as synchronous (the ERTYPE pin is high), the
SEMI asserts EROMN for two instruction cycles (one ECKO cycle
) for a read or write operation
.
The SEMI is not selecting the EROM memory component for a read access.
The SEMI 3-states EROMN if it grants a request by an external device to access the external mem-
ory (see description of the EREQN pin in
Table 53 on page 102
).
1
Z
If any memory component is configured as synchronous, ECKO must be programmed as CLK/2, i.e., the ECKO[1:0] field (
ECON1
[1:0]—
Table 60 on
page 110
) must be programmed to 0x0.
The SEMI can write the EROM component only if the WEROM field (
ECON1
[11]—see
Table 60 on page 110
) is set.
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