
Data Sheet
June 2001
DSP16410B Digital Signal Processor
114
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
4 Hardware Architecture
(continued)
4.14 System and External Memory Interface (SEMI)
(continued)
4.14.5 Asynchronous Memory
(continued)
4.14.5.1 Functional Timing
(continued)
Figures
27
through
30
provide examples of asynchronous memory accesses for various SEMI configurations.
These examples assume that the DMAU is performing the external memory accesses. The access rate shown is
not achievable if the accesses are performed by one or both cores. For details on SEMI performance for an asyn-
chronous interface, see
Section 4.14.7.2 on page 126
. For a summary of SEMI performance, see
Section 4.14.7.4
on page 130
.
Asynchronous Timing
Notes:
It is assumed that ECKO is programmed as CLK, i.e., the ECKO[1:0] field (
ECON1
[1:0]—
Table 60 on page 110
) is programmed to 0x1.
It is assumed that the YATIME[3:0] field (
ECON0
[7:4]—
Table 59 on page 109
) is programmed to 0x2 and the IATIME[3:0] field (
ECON0
[11:8]) is
programmed to 0x3.
It is assumed that the DMAU is performing the external memory accesses. The access rate shown is not achievable if the accesses are per-
formed by one or both cores.
Figure 27. Asynchronous Memory Cycles
EION
ERWN
ECKO
ERAMN
DON’T CARE
HIGH-IMPEDANCE OUTPUT
ERAM
READ
ERAM
READ
IDLE CYCLE: WRITE FOLLOWED IMMEDIATELY BY READ
ERAM
READ
ERAM
WRITE
ERAM
WRITE
EIO
READ
EIO
WRITE
IATIME
A5
A4
A6
A3
A2
A1
A0
EA
D1
D2
D6
Q3
Q4
Q5
ED
Q0
YATIME
YATIME
YATIME
YATIME
YATIME
IATIME