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參數(shù)資料
| 型號(hào)： | DSP16410C |
| 英文描述： | TVS 400W 7.0V UNIDIRECT SMA |
| 中文描述： | DSP1629數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 111/373頁(yè) |
| 文件大?。?/td> | 5643K |
| 代理商： | DSP16410C |
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Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
55
4 Hardware Architecture
(continued)
4.10 Timer Units (TIMER0_
0—1
and TIMER1_
0—1
)
(continued)
Table 21. timer
0,1
(TIMER
0,1
Running Count) Register
4.11 Hardware Development System
(HDS
0—1
)
The DSP16410B provides an on-chip hardware devel-
opment module for each of the two cores (HDS
0—1
).
Each HDS is available for debugging assembly-
language programs that execute on the DSP16000
core at the core’s rated speed. The main capability of
the HDS is allowing controlled visibility into the core’s
state during program execution.
The fundamental steps in debugging an application
using the HDS include the following:
1. Setup: Download program code and data into the
correct memory regions and set breakpointing con-
ditions.
2. Run: Start execution or single step from a desired
starting point (i.e., allow device to run under simu-
lated or real-time conditions).
3. Break: Break program execution on satisfying break-
pointing conditions; upload and allow user accessi-
bility to internal state of the device and its pins.
4. Resume: Resume execution (normally or single
step) after hitting a breakpoint and finally upload
internal state at the end of execution.
A powerful debugging capability of the HDS is the abil-
ity to break program execution on complex breakpoint-
ing conditions. A complex breakpoint condition, for
example, can be an instruction that executes from a
particular instruction-address location (or from a partic-
ular instruction-address range such as a subroutine)
and accesses a coefficient/data element from a spe-
cific memory location (or from a memory region such
as inside an array or outside an array). Complex condi-
tions can also be chained to form more complex break-
point conditions. For example, a complex breakpoint
condition can be defined as the back-to-back execution
of two different subroutines.
The HDS also provides a debugging feature that allows
a number of complex breakpoints to be ignored. The
number of breakpoints ignored is programmable by the
user.
An intelligent trace mechanism for recording disconti-
nuity points during program execution is also available
in the HDS. This mechanism allows unambiguous
reconstruction of program flow involving discontinuity
points such as gotos, calls, returns, and interrupts. The
trace mechanism compresses single-level (non-
nested) loops and records them as a single discontinu-
ity. This feature prevents single-level loops from filling
up the trace buffers. Also, cache loops do not get reg-
istered as discontinuities in the trace buffers. There-
fore, two-level loops with inner cache loops are
registered as a single discontinuity.
The HDS provides a 32-bit cycle counter for accurate
code profiling during program development. The cycle
counter records processor CLK cycles between user-
defined start and end points. The cycle counter can
optionally be used to break program execution after a
user-specified number of clock cycles.
15—0
TIMER
0,1
Down Counter
TIMER
0,1
Period Register
Bit
Field
If the user program writes to the
timer
0,1
register, TIMER
0,1
loads the 16-bit write value into the down counter and into the period register
simultaneously. If the user program reads the
timer
0,1
register, TIMER
0,1
returns the current 16-bit value from the down counter.
To read or write the
timer
0,1
register, TIMER
0,1
must be powered up, i.e., the PWR_DWN field (
timer
0,1
c
[6]) must be cleared.
§ For this column, X indicates unknown on powerup reset and unaffected on subsequent reset.
Description
R/W
Reset
Value
§
0
15—0
Down Counter
If the COUNT field (
timer
0,1
c
[4]) is set, TIMER
0,1
decrements this portion
of the
timer
0,1
register every prescale period. When the down counter
reaches zero, TIMER
0,1
generates an interrupt.
Period Register
If the COUNT field (
timer
0,1
c
[4]) and the RELOAD field (
timer
0,1
c
[5]) are
both set and the down counter contains zero, TIMER
0,1
reloads the down
counter with the contents of this portion of the
timer
0,1
register.
R/W
15—0
W
X
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