
Data Sheet
June 2001
DSP16410B Digital Signal Processor
164
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
4 Hardware Architecture
(continued)
4.16 Serial Interface Unit (SIU)
(continued)
4.16.6 ST-Bus Timing Examples
(continued)
Figure 46
illustrates the functional timing of the internally generated bit clocks and frame syncs, ICK, OCK, IFS,
and OFS, assuming the bit clock divide ratio is two (AGCKLIM = 1, same as
Figure 45 on page 163
) and SIFS is
asserted while the internally generated bit clocks are high. In this case, the internal bit clocks are forced to remain
high at the falling edge of SIFS. This effectively stretches the internal bit clocks by one SCK cycle, synchronizing
the internal bit clocks to the external frame sync, SIFS. As a result, the first frame following synchronization is
lost. The SIU 3-states the SOD pin during the lost frame. Subsequent frames are synchronized and function cor-
rectly. The dotted lines in this figure show the location of SIFS and the active bit clocks and syncs if SIFS had
occurred one SCK cycle later (i.e., if the internal frame bit counter had expired prior to the assertion of SIFS, the
same as
Figure 45
).
Clock and Frame Sync Generation with External Clock and Synchronization
(AGCKLIM = 1, SCKK = 1, IFSK = 1, SIFS Causes Resynchronization)
Figure 46. Clock and Frame Sync Generation with External Clock and Synchronization
(AGEXT = AGSYNC = IFSA = IFSK = 1 and Timing Requires Resynchronization)
SCK
OCK
SIFS
ICK
OFS
IFS
SOD
B
N
B
N – 1
B
N – 2
THIS FRAME IS LOST