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參數(shù)資料
| 型號(hào)： | DSP16410C |
| 英文描述： | TVS 400W 7.0V UNIDIRECT SMA |
| 中文描述： | DSP1629數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 81/373頁(yè) |
| 文件大?。?/td> | 5643K |
| 代理商： | DSP16410C |
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Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
25
4 Hardware Architecture
(continued)
4.4 Interrupts and Traps
Each core in the DSP16410B supports the following
interrupts and traps:
26 hardware interrupts with three levels of user-
assigned priority:
—1 core-to-core interrupt.
—10 general DMAU interrupts.
—1 DMAU interrupt under control of the other core.
—4 SIU interrupts.
—3 PIU interrupts.
—1 MGU interrupt.
—2 timer interrupts.
—4 external interrupt pins.
64 software interrupts for each core, generated by
the execution of an
icall IM6
instruction.
The TRAP pin.
The core-to-core trap.
Because the DSP16000 core supports a maximum of
20 hardware interrupts and the DSP16410B provides
26 hardware interrupts, each core has an associated
programmable interrupt multiplexer (IMUX
0,1
).
The interrupt and trap vectors are in contiguous loca-
tions in memory, and the base (starting) address of the
vectors is configurable in the core’s
vbase
register.
Each interrupt and trap source is preassigned to a
unique vector offset that differentiates its service rou-
tine.
The core must reach an interruptible or trappable state
(completion of an interruptible or trappable instruction)
before it services an interrupt or trap. If the core ser-
vices an interrupt or trap, it saves the contents of its
program counter (
PC
) and begins executing instruc-
tions at the corresponding location in its vector table.
For interrupts, the core saves its
PC
in its program
interrupt (
pi
) register. For traps, the core saves its
PC
in its program trap (
ptrap
) register. After servicing the
interrupt or trap, the servicing routine must return to the
interrupted or trapped program by executing an
ireturn
or
treturn
instruction.
The core’s
ins
register (see
Table 8 on page 32
) con-
tains a 1-bit status field for each of its hardware inter-
rupts. If a hardware interrupt occurs, the core sets the
corresponding
ins
field to indicate that the interrupt is
pending. If the core services that interrupt, it clears the
corresponding
ins
field. The
psw1
register (see
Table 10 on page 35
) includes control and status bits
for the core’s hardware interrupt logic.
If a hardware interrupt is disabled, the core does not
service it. If a hardware interrupt is enabled, the core
services it according to its priority. Device reset glo-
bally disables hardware interrupts. An application can
globally
1
enable or disable hardware interrupts and can
individually enable or disable each hardware interrupt.
An application globally enables hardware interrupts by
executing the
ei
(enable interrupts) instruction and glo-
bally disables them by executing the
di
(disable inter-
rupts) instruction. An application can individually
enable a hardware interrupt at an assigned priority or
individually disable a hardware interrupt by configuring
the
inc0
or
inc1
register (see
Table 7 on page 31
).
Software interrupts emulate hardware interrupts for the
purpose of software testing. The core services soft-
ware interrupts even if hardware interrupts are globally
disabled.
A trap is similar to an interrupt but has the highest pos-
sible priority. An application cannot disable traps by
executing a
di
instruction or by any other means. Traps
do not nest, i.e., a trap service routine (TSR) cannot be
interrupted or trapped. A trap does not affect the state
of the
psw1
register.
The DSP16000 Digital Signal Processor CoreInforma-
tion Manual provides an extensive discussion of inter-
rupts and traps. The remainder of this section
describes the interrupts and traps for the DSP16410B.
4.4.1 Hardware Interrupt Logic
Figure 3 on page 26
illustrates the path of each inter-
rupt from its generating peripheral or pin to the interrupt
logic of CORE0 and CORE1. Some of the interrupts
connect directly to the cores, and others connect via
the IMUX
0,1
block. Some of the interrupts are spe-
cific to a core, and some are common to both cores.
The programmer can configure IMUX
0,1
using the
corresponding
imux
register. The programmer can
divide processing of the multiplexed interrupts PIBF,
POBE, S
O
,
I
INT
0,1
, DSINT[3:0], DDINT[3:0],
DMINT[5:4], INT[3:2] between CORE0 and CORE1 or
cause some of these interrupts to be common to both
cores by defining the fields in each core’s
imux
regis-
ter. See
Section 4.4.2 on page 28
for details on inter-
rupt multiplexing.
1. A program that runs on one core disables and enables its interrupts independent of the other core.
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