Data Sheet
June 2001
DSP16410B Digital Signal Processor
240
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
6 Software Architecture
(continued)
6.2 Registers
(continued)
6.2.3 Register Encodings
(continued)
Table 154. pllcon (Phase-Lock Loop Control) Register
Note: pllcon
is accessible in CORE0 only.
15—2
Reserved
Table 155. pllfrq (Phase-Lock Loop Frequency Control) Register
Note: pllfrq
is accessible in CORE0 only.
15—14
OD[1:0]
Table 156. plldly (Phase-Lock Loop Delay Control) Register
Note: plldly
is accessible in CORE0 only.
1
0
PLLEN
PLLSEL
Bit
15—2
1
Field
Reserved
PLLEN
Value
—
0
1
0
1
Description
R/W
R/W
R/W
Reset Value
0
0
Reserved—write with zero.
Disable (power down) the PLL.
Enable (power up) the PLL.
Select the CKI input as the internal clock (CLK) source.
Select the PLL as the internal clock (CLK) source.
0
PLLSEL
R/W
0
13—9
D[4:0]
8—0
M[8:0]
Bit
Field
OD[1:0]
Value
00
01
10
11
0—31
0—511
Description
R/W
R/W
Reset Value
00
15—14
f(OD) = 2. Divide VCO output by 2.
f(OD) = 4. Divide VCO output by 4.
f(OD) = 4. Divide VCO output by 4.
f(OD) = 8. Divide VCO output by 8.
Divide f
CKI
by this value plus two (D + 2).
Multiply f
CKI
by this value plus two (M + 2).
13—9
8—0
D[4:0]
M[8:0]
R/W
R/W
00000
000000000
15—0
DLY[15:0]
Bit
15—0
15—0
DLY[15:0]
Value
—
Description
R/W
R/W
Reset Value
0x1388
The contents of DLY[15:0] is loaded into the PLL delay
counter after a
pllcon
register write. If PLLEN
(
pllcon
[1]) is 1, the counter decrements each CKI cycle.
When the counter reaches zero, the LOCK
flag
for both
CORE0 and CORE1 is asserted.
The state of the LOCK flag can be tested by conditional instructions (
Table 134 on page 223
) and is also visible in the
alf
register (
Table 140 on
page 232
). The LOCK flag is cleared by a device reset or a write to the
pllcon
register.