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參數(shù)資料
| 型號(hào)： | DSP16410C |
| 英文描述： | TVS 400W 7.0V UNIDIRECT SMA |
| 中文描述： | DSP1629數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 76/373頁(yè) |
| 文件大小： | 5643K |
| 代理商： | DSP16410C |
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Data Sheet
June 2001
DSP16410B Digital Signal Processor
20
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
4 Hardware Architecture
(continued)
4.2 DSP16000 Core Architectural
Overview
(continued)
4.2.2 Data Arithmetic Unit (DAU)
(continued)
The DAU contains control and status registers
auc0
,
auc1
,
psw0
,
psw1
,
vsw
, and
c0
—
c2
.
The arithmetic unit control registers
auc0
and
auc1
select or deselect various modes of DAU operation.
These modes include scaling of products, saturation on
overflow, feedback to the
x
and
y
registers from accu-
mulators
a6
and
a7
, simultaneous loading of
x
and
y
registers with the same value (used for single-cycle
squaring), and clearing the low half of registers when
loading the high half to facilitate fixed-point operations.
The processor status word registers
psw0
and
psw1
contain flags set by ALU/ACS, ADDER, or BMU opera-
tions. They also include information on the current sta-
tus of the interrupt controller.
The
vsw
register is the Viterbi support word associated
with the traceback encoder. The traceback encoder is a
specialized block for accelerating Viterbi decoding. The
vsw
controls side-effects for three compare functions:
cmp0( )
,
cmp1( )
, and
cmp2( )
. These instructions are
part of the MAC group that utilizes the traceback
encoder. The side-effects allow the DAU to store, with
no overhead, state information necessary for traceback
decoding. Side-effects use the
c1
counter, the
ar0
and
ar1
auxiliary registers, and bits 1 and 0 of
vsw
.
The
c1
and
c0
counters are 16-bit signed registers
used to count events such as the number of times the
program has executed a sequence of code. The
c2
register is a holding register for counter
c1
. Conditional
instructions control these counters and provide a con-
venient method of program looping.
4.2.3 Y-Memory Space Address Arithmetic Unit
(YAAU)
The YAAU supports high-speed, register-indirect, data
memory addressing with postincrement of the address
register. Eight 20-bit pointer registers (
r0
—
r7
) store
read or write addresses for the data (Y-memory) space.
Two sets of 20-bit registers (
rb0
and
re0
;
rb1
and
re1
)
define the upper and lower boundaries of two zero-
overhead circular buffers for efficient filter implementa-
tions. The
j
and
k
registers are two 20-bit signed regis-
ters that are used to hold user-defined postincrement
values for
r0
—
r7
. Fixed increments of +1, –1, 0, +2,
and –2 are also available. (Postincrement options 0 and
–2 are not available for some specialized transfers. See
the DSP16000 Digital Signal Processor Core Informa-
tion Manual for details.)
The YAAU includes a 20-bit stack pointer (
sp
). The
data move group includes a set of stack instructions
that consists of push, pop, stack-relative, and pipelined
stack-relative operations. The addressing mode used
for the stack-relative instructions is register-plus-dis-
placement indirect addressing (the displacement is
optional). The displacement is specified as either an
immediate value as part of the instruction or a value
stored in
j
or
k
. The YAAU computes the address by
adding the displacement to
sp
and leaves the contents
of
sp
unchanged. The data move group also includes
instructions with register-plus-displacement indirect
addressing for the pointer registers
r0
—
r6
in addition to
sp
.
The data move group of instructions includes instruc-
tions for loading and storing any YAAU register from or
to memory or another core register. It also includes
instructions for loading any YAAU register with an
immediate value stored with the instruction. The
pointer arithmetic group of instructions allows adding of
an immediate value or the contents of the
j
or
k
register
to any YAAU pointer register and storing the result to
any YAAU register.
4.2.4 X-Memory Space Address Arithmetic Unit
(XAAU)
The XAAU contains registers and an adder that control
the sequencing of instructions in the processor. The
program counter (
PC
) automatically increments
through the instruction space. The interrupt return reg-
ister
pi
, the subroutine return register
pr
, and the trap
return register
ptrap
are automatically loaded with the
return address of an interrupt service routine, subrou-
tine, and trap service routine, respectively. High-speed,
register-indirect, read-only memory addressing with
postincrementing is done with the
pt0
and
pt1
regis-
ters. The signed registers
h
and
i
are used to hold a
user-defined signed postincrement value. Fixed postin-
crement values of 0, +1, –1, +2, and –2 are also avail-
able. (Postincrement options 0 and –2 are available
only if the target of the data transfer is an accumulator.
See the DSP16000 Digital Signal Processor Core nfor-
mation Manual for details.)
The data move group includes instructions for loading
and storing any XAAU register from or to memory or
another core register. It also includes instructions for
loading any XAAU register with an immediate value
stored with the instruction.
vbase
is the 20-bit vector base offset register. The user
programs this register with the base address of the
interrupt and trap vector table.
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