
Data Sheet
June 2001
DSP16410B Digital Signal Processor
272
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
10 Electrical Characteristics and Requirements
(continued)
10.3 Power Dissipation
(continued)
10.3.2 I/O Power Dissipation
I/O power dissipation is highly dependent on operating voltage, I/O loading, and I/O signal frequency. It can be
estimated as:
where C
L
is the load capacitance, V
DD
2 is the I/O supply voltage, and f is the frequency of output signal.
Table 180
lists the estimated typical I/O power dissipation contribution for each output and I/O pin for a typical appli-
cation under specific conditions. The following conditions are assumed for all cases:
I
V
DD
2 is 3.3 V.
I
The load capacitance for each output and I/O pin is 30 pF.
For applications with values of C
L
, V
DD
2, or f that differ from those assumed for
Table 180
, the above formula can
be used to adjust the I/O power dissipation values in the table.
Table 180. Typical I/O Power Dissipation at 3.3 V
Internal
Peripheral
SEMI
Pin(s)
Type
No. of
Pins
32
2
1
18
4
1
1
1
1
14
16
1
1
1
1
2
2
2
2
2
Signal Frequency
(MHz)
CLK/4
CLK/4
CLK/8
CLK/4
CLK/4
CLK/12
CLK/12
CLK/12
CLK/2
1
30
1
30
30
30
8
8
8
0.03
0.03
I/O Power Dissipation (mW)
170 MHz
222
13.8
6.9
250
56
4.6
4.6
4.6
27.2
4.6
78.5
0.33
9.8
9.8
9.8
5.2
5.2
5.2
0.019
0.019
185 MHz
242
15
7.6
273
60
5.1
5.1
5.1
30.2
4.6
78.5
0.33
9.8
9.8
9.8
5.2
5.2
5.2
0.019
0.019
Assumptions: The SEMI is configured for a 32-bit external data bus (the ESIZE pin is high). The contribution from the EACKN pin is
negligible.
Assumption: the pins switch from input to output at a 50% duty cycle.
§ Assumption: the corresponding core has configured these pins as outputs.
ED[31:0]
ERWN[1:0]
EA0
EA[18:1]
ESEG[3:0]
EROMN
ERAMN
EION
ECKO
IO
0—1
BIT[6:0]
PD[15:0]
PINT
PIBF
POBE
PRDY
SICK
0—1
SOCK
0—1
SOD
0—1
SIFS
0—1
SOFS
0—1
I/O
O
O
O
O
O
O
O
O
O
§
I/O
O
O
O
O
O
O
O
O
O
BIO
0—1
PIU
SIU
0—1
C
L
V
DD
2
2
f