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參數(shù)資料
| 型號(hào)： | DSP16410C |
| 英文描述： | TVS 400W 7.0V UNIDIRECT SMA |
| 中文描述： | DSP1629數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 319/373頁(yè) |
| 文件大?。?/td> | 5643K |
| 代理商： | DSP16410C |
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Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
263
8 Signal Descriptions
(continued)
8.6 PIU Interface
(continued)
PRWN—PIU Read/Write Not:
Input. Function is
dependent upon the host type (Intelor Motorola). In
either case, PRWN is driven high by the host during
host reads and driven low by the host during host
writes. PRWN must be stable for the entire access
(while PCSN and the appropriate data strobe are
asserted). If unused, PRWN must be tied high.
Intelmode: In this mode, PRWN is connected to the
active-low write data strobe of the host processor,
the same as the PIDS input.
Motorola mode: In this mode, PRWN functions as an
active read/write strobe and must be connected to
the RWN output of the Motorolahost processor.
PCSN—PIU Chip Select:
Negative-assertion input.
PCSN is the chip select from the host for shared-bus
systems. If PCSN = 0, the PIU of the selected
DSP16410B is active for transfers with the host. If
PCSN = 1, the PIU ignores any activity on PIDS,
PODS, and PRWN and 3-states PD[15:0]. If unused,
PCSN must be tied high.
8.7 JTAG0 Test Interface
The JTAG0 test interface has features that allow pro-
grams and data to be downloaded into CORE0 via five
pins. This provides extensive test and diagnostic capa-
bility. In addition, internal circuitry allows the device to
be controlled through the JTAG port to provide on-chip,
in-circuit emulation. Agere Systems provides hardware
and software tools to interface to the on-chip HDS via
the JTAG port.
Note:
JTAG0 provides all JTAG/IEEE1149.1 standard
test capabilities including boundary scan.
TDI0—JTAG Test Data Input:
Serial input signal. All
serial-scanned data and instructions are input on this
pin. This pin has an internal pull-up resistor.
TDO0—JTAG Test Data Output:
Serial output signal.
Serial-scanned data and status bits are output on this
pin.
TMS0—JTAG
Test Mode Select:
Mode control signal
that, combined with TCK0, controls the scan opera-
tions. This pin has an internal pull-up resistor.
TCK0—JTAG Test Clock:
Serial shift clock. This sig-
nal clocks all data into the port through TDI0 and out of
the port through TDO0. It also controls the port by
latching the TMS0 signal inside the state-machine con-
troller.
TRST0N—JTAG
TAP Controller Reset:
Negative
assertion. Test reset. If asserted low, resets the
JTAG0 TAP controller. In an application environment,
this pin must be asserted prior to or concurrent with
RSTN. This pin has an internal pull-up resistor.
8.8 JTAG1 Test Interface
The JTAG1 test interface has features that allow pro-
grams and data to be downloaded into CORE1 via five
pins. This provides extensive test and diagnostic capa-
bility. In addition, internal circuitry allows the device to
be controlled through the JTAG port to provide on-chip,
in-circuit emulation. Agere Systems provides hard-
ware and software tools to interface to the on-chip HDS
via the JTAG port.
Note:
JTAG1 provides all JTAG/IEEE 1149.1 standard
test capabilities including boundary scan.
TDI1—JTAG Test Data Input:
Serial input signal. All
serial-scanned data and instructions are input on this
pin. This pin has an internal pull-up resistor.
TDO1—JTAG Test Data Output:
Serial output signal.
Serial-scanned data and status bits are output on this
pin.
TMS1—JTAG
Test Mode Select:
Mode control signal
that, combined with TCK1, controls the scan opera-
tions. This pin has an internal pull-up resistor.
TCK1—JTAG Test Clock:
Serial shift clock. This sig-
nal clocks all data into the port through TDI1 and out of
the port through TDO1. It also controls the port by
latching the TMS1 signal inside the state-machine con-
troller.
TRST1N—JTAG
TAP Controller Reset:
Negative
assertion. Test reset. If asserted low, TRST1N resets
the JTAG1 TAP controller. In an application environ-
ment, this pin must be asserted prior to or concurrent
with RSTN. This pin has an internal pull-up resistor.
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