Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
93
4 Hardware Architecture
(continued)
4.13 Direct Memory Access Unit
(DMAU)
(continued)
4.13.8 Error Reporting and Recovery
Each of the ERR[5:0] fields of the
DSTAT
register
(
Table 30 on page 68
) reflects a DMAU protocol failure
that indicates a loss of data for the corresponding
channel. For the SWT
0—3
channels, the DMAU sets
the corresponding ERR[3:0] field if:
An SIU
0—1
requests DMAU service for a channel
before the DMAU has accepted the previous request
from that SIU
0—1
for that channel.
An SIU
0—1
requests DMAU service for a channel
and that channel’s RESET[3:0] field
(
DMCON1
[3:0]—
Table 32 on page 71
) is set.
An SIU
0—1
requests DMAU destination/source
service for a channel and that channel’s
DRUN[3:0]/SRUN[3:0] field
(
DMCON0
[7:0]—
Table 31 on page 70
) is cleared.
An SIU
0—1
requests DMAU service for a channel
and that channel’s source/destination transfer is
complete (
SCNT
0—3
/DCNT
0—3
= LIM
0—3
)
and that channel’s AUTOLOAD field
(
CTL
0—3
[0]—
Table 34 on page 73
) is cleared.
For the MMT
4—5
channels, the DMAU sets the cor-
responding ERR[5:4] field if:
The user software attempts to set the TRIGGER[5:4]
field by writing 1 to
DMCON0
[11:10] and the
TRIGGER[5:4] field is already set.
The user software attempts to set the TRIGGER[5:4]
field by writing 1 to
DMCON0
[11:10] and the
RESET[5:4] field (
DMCON1
[5:4]) is set.
If servicing a DMAU channel interrupt, the user soft-
ware should poll
DSTAT
to determine whether an error
has occurred. If so, the user software must perform the
following steps:
1. Set the corresponding RESET[5:0] field
(
DMCON1
[5:0]) to terminate all channel activity.
2. Write a 1 to the corresponding ERR[5:0] field to
clear the field and the error condition.
3. Reinitialize the corresponding channel address and
count registers.
4. Clear the corresponding RESET[5:0] field to re-allow
channel activity.
5. For an MMT channel, re-enable a channel transfer
by setting the appropriate TRIGGER[5:4] field
(
DMCON0
[11:10]).