Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
229
6 Software Architecture
(continued)
6.2 Registers
(continued)
6.2.2 Memory-Mapped Registers
(continued)
Table 136
summarizes the DMAU memory-mapped registers. These registers are described in detail in
Section 4.13.2 on page 66
.
Table 136. DMAU Memory-Mapped Registers
Type
Register
Name
DSTAT
DMCON0
DMCON1
CTL0
CTL1
CTL2
CTL3
CTL4
CTL5
SADD0
DADD0
SADD1
DADD1
SADD2
DADD2
SADD3
DADD3
SADD4
DADD4
SADD5
DADD5
SCNT0
DCNT0
SCNT1
DCNT1
SCNT2
DCNT2
SCNT3
DCNT3
SCNT4
DCNT4
SCNT5
DCNT5
Channel
Address
Size
(Bits)
32
16
R/W
Type
Signed/
Unsigned
unsigned
unsigned
Reset
Value
X
0
DMAU Status
DMAU Master Control 0
DMAU Master Control 1
Channel Control
All
All
All
0x4206C
0x4205C
0x4205E
0x42060
0x42062
0x42064
0x42066
0x42068
0x4206A
0x42000
0x42002
0x42004
0x42006
0x42008
0x4200A
0x4200C
0x4200E
0x42010
0x42012
0x42014
0x42016
0x42020
0x42022
0x42024
0x42026
0x42028
0x4202A
0x4202C
0x4202E
0x42030
0x42032
0x42034
0x42036
R
status
control
R/W
SWT0
SWT1
SWT2
SWT3
MMT4
MMT5
SWT0
16
R/W
control
unsigned
X
Source Address
Destination Address
Source Address
Destination Address
Source Address
Destination Address
Source Address
Destination Address
Source Address
Destination Address
Source Address
Destination Address
Source Count
Destination Count
Source Count
Destination Count
Source Count
Destination Count
Source Count
Destination Count
Source Count
Destination Count
Source Count
Destination Count
For this column, X indicates unknown on powerup reset and unaffected on subsequent reset. Any reserved fields within the register are reset to zero.
The reindex registers are in sign-magnitude format.
32
R/W
address
unsigned
X
SWT1
SWT2
SWT3
MMT4
MMT5
SWT0
20
R/W
data
unsigned
X
SWT1
SWT2
SWT3
MMT4
MMT5