Data Sheet
June 2001
DSP16410B Digital Signal Processor
184
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
4 Hardware Architecture
(continued)
4.16 Serial Interface Unit (SIU)
(continued)
4.16.15 Registers
(continued)
Table 103. SCON2 (SIU Output Frame Control) Register
The memory address for this register is 0x43004 for SIU0 and 0x44004 for SIU1.
15—11
10
Reserved
ORESET
9—8
7
6—0
OFSDLY[1:0]
OFRAME
OFLIM[6:0]
Bit
Field
Value
Description
R/W
Reset
Value
0
1
15—11
10
Reserved
ORESET
0
0
Reserved—write with zero.
Activate output section, request output service from the DMAU, and drive SOD
pin at the start of the first active output channel.
Deactivate output section and initialize bit and frame counters.
No output frame sync delay—drive output data onto SOD pin starting with the
same internal bit clock (OCK) that latches the output frame sync (SOFS pin for
passive sync or OFS signal for active generated sync).
One-cycle output frame sync delay—drive output data onto SOD pin starting
one bit clock (OCK) after the bit clock that latches the output frame sync
(SOFS pin for passive sync or OFS signal for active generated sync).
Two-cycle output frame sync delay—drive output data onto SOD pin starting
two bit clocks (OCK) after the bit clock that latches output frame sync (SOFS
pin for passive sync or OFS signal for active generated sync).
Reserved.
Channel mode—base the output transfer decision on the OSFIDV_E field
(
SCON3
[10]), the OSFVEC_E[15:0] field (
SCON6
[15:0]), the OSFIDV_O field
(
SCON3
[13]), and the OSFVEC_O[15:0] field (
SCON7
[15:0]).
Frame mode—transmit all OFLIM + 1 channels in the frame.
0—127 Output frame channel count limit—the number of channels in the output frame
is OFLIM + 1.
R/W
R/W
1
00
9—8
OFSDLY[1:0]
R/W
00
01
10
11
0
7
OFRAME
R/W
0
1
6—0
OFLIM[6:0]
R/W
0
If the ORESET field (
SCON2
[10]) is cleared, do not change the value in this field.