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參數(shù)資料
| 型號(hào)： | DSP16410C |
| 英文描述： | TVS 400W 7.0V UNIDIRECT SMA |
| 中文描述： | DSP1629數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 196/373頁(yè) |
| 文件大?。?/td> | 5643K |
| 代理商： | DSP16410C |
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Data Sheet
June 2001
DSP16410B Digital Signal Processor
140
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
4 Hardware Architecture
(continued)
4.15 Parallel Interface Unit (PIU)
(continued)
4.15.3 Host Data Read and Write Cycles
This section describes typical host read and write
cycles of data for both Inteland Motorolahosts.
Figure 38 on page 141
is a functional timing diagram of
a data read and a data write cycle for both an Inteland
a Motorolahost. The address that the host applies to
PADD[3:0] during the cycle determines the transaction
type, i.e., determines the host command. See
Section
4.15.5 on page 144
for details on host commands.
The following sequence corresponds to the Intel data
read cycle shown in
Figure 38
:
1. The host drives a valid address onto PADD[3:0].
The host must hold PIDS high for the entire duration
of the access.
2. The host initiates the cycle by asserting (low) PCSN
and PODS.
3. When data becomes available in
PDO
, the PIU
drives the data onto PD[15:0].
4. To notify the host that the data in
PDO
and on
PD[15:0] is valid, the PIU asserts PRDY and deas-
serts POBE. If the data in
PDO
is not yet valid, the
PIU continues deasserting PRDY and the host must
wait until the PIU asserts PRDY.
5. The host concludes the cycle by deasserting PCSN
or PODS and latching the data from PD[15:0].
6. The PIU 3-states PD[15:0].
The following sequence corresponds to the Intel data
write cycle shown in
Figure 38
:
1. The host drives a valid address onto PADD[3:0].
The host must hold PODS high for the entire dura-
tion of the access.
2. The host initiates the cycle by asserting (low) PCSN,
PIDS, and PRWN.
3. The host drives data onto PD[15:0].
4. If
PDI
is empty, the PIU notifies the host by asserting
PRDY and deasserting PIBF. If
PDI
is still full from a
previous host write, the host must wait until the PIU
asserts PRDY.
5. The host concludes the cycle by deasserting PCSN
or PIDS, causing the PIU to latch the data from
PD[15:0] into
PDI
.
6. The host 3-states PD[15:0].
The following sequence corresponds to the Motorola
data read cycle shown in
Figure 38
. In the figure and in
the timing sequences described below, it is assumed
that PIDS is tied high, selecting an active-low data
strobe (PODS).
1. The host drives a valid address onto PADD[3:0].
The host must hold PRWN high for the duration of
the access.
2. The host initiates the cycle by asserting PCSN and
PODS (low).
3. When data becomes available in
PDO
, the PIU
drives the data onto PD[15:0].
4. To notify the host that the data in
PDO
and on
PD[15:0] is valid, the PIU asserts PRDY and deas-
serts POBE. If the data in
PDO
is not yet valid, the
PIU continues deasserting PRDY and the host must
wait until the PIU asserts PRDY.
5. The host concludes the cycle by deasserting PCSN
or PODS and latching the data from PD[15:0].
6. The PIU 3-states PD[15:0].
The following sequence corresponds to the Motorola
data write cycle shown in
Figure 38
. In the figure and
in the timing sequences described below, it is assumed
that PIDS is tied high, selecting an active-low data
strobe (PODS).
1. The host drives a valid address onto PADD[3:0] and
drives PRWN low.
2. The host initiates the cycle by asserting PCSN and
PODS (low).
3. The host drives data onto PD[15:0].
4. If
PDI
is empty, the PIU notifies the host by asserting
PRDY and deasserting PIBF. If
PDI
is still full from a
previous host write, the host must wait until the PIU
asserts PRDY.
5. The host concludes the cycle by deasserting PCSN
or PODS, causing the PIU to latch the data from
PD[15:0] into
PDI
.
6. The host 3-states PD[15:0].
Note:
Once the host initiates a data read or data write
transaction, it must complete it properly as
described above. If the host concludes the
transaction before the PIU asserts PRDY, the
results are undefined and the PIU must be
reset. In this case, the host can reset the PIU by
setting the HRESET field (
PCON
[5]—
Table 73
on page 133
) or a core can reset the PIU by set-
ting the DRESET field (
PCON
[6]).
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