- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄376460 > XRT7245 (Exar Corporation) DS3 ATM User Network Interface(DS3異步傳輸模式用戶網(wǎng)絡(luò)接口) PDF資料下載
參數(shù)資料
| 型號(hào)： | XRT7245 |
| 廠商： | Exar Corporation |
| 英文描述： | DS3 ATM User Network Interface(DS3異步傳輸模式用戶網(wǎng)絡(luò)接口) |
| 中文描述： | DS3自動(dòng)柜員機(jī)用戶網(wǎng)絡(luò)接口（DS3異步傳輸模式用戶網(wǎng)絡(luò)接口） |
| 文件頁(yè)數(shù)： | 97/324頁(yè) |
| 文件大小： | 4103K |
| 代理商： | XRT7245 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)當(dāng)前第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)第305頁(yè)第306頁(yè)第307頁(yè)第308頁(yè)第309頁(yè)第310頁(yè)第311頁(yè)第312頁(yè)第313頁(yè)第314頁(yè)第315頁(yè)第316頁(yè)第317頁(yè)第318頁(yè)第319頁(yè)第320頁(yè)第321頁(yè)第322頁(yè)第323頁(yè)第324頁(yè)
á
PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
97
Receive Cell Processor, upon identifying an incoming
OAM cell, will copy the header and payload contents
of this cell to the “Received OAM Cell” buffer (in on-
chip RAM). If the user does not configure the Receive
Cell processor to perform an “OAM Cell Check”, the
OAM cell will simply be treated like any other user
cell, as it is processed through the User Cell Filter,
where it can be discarded or written to the Rx FIFO.
Writing a “0” to this bit-field disables the OAM Cell
Check feature. Writing a “1” to this bit-field enables
this feature.
Bit 2–De-Scramble Enable
This “Read/Write” bit-field allows the user to enable
or disable the Cell Descrambler, within the Receive
Cell Processor. When the Cell Descrambler is en-
abled, the Receive Cell Processor will “presume” that
the payload portion of each incoming cell has been
scrambled by the “far-end” Transmit Cell Processor.
Therefore, the Receive Cell Processor will modify the
contents of the cell payload accordingly. If the Cell
Descrambler is disabled, then the Receive Cell Pro-
cessor will perform NO modifications to the payload,
of the incoming cells, at all.
Writing a “0” to this bit-field disables the Cell De-
Scrambler. Writing a “1” to this bit-field enables the
Cell Descrambler.
For more information on Cell Scrambling and Cell
Descrambling, please see Sections 6.2.2.2 and
7.3.2.5.
Bit 1—Rx Coset Enable
This “Read/Write” bit-field allows the user to config-
ure the Receive Cell Processor to account for (or not
to account for) the “far-end” Transmit Cell Processor’s
modulo-2 addition of the Coset polynomial: x
6
+ x
4
+
x
2
+ 1 to the “original” HEC byte, during HEC byte cal-
culation and insertion.
If the user configures the Receive Cell Processor to
account for the Coset Polynomial, then the Receive
Cell Processor will go through the following procedure
during HEC byte verification:
Recompute the “Original” HEC (CRC-8) byte,
based upon the values of bytes 1 through 4 in the
received cell.
Modulo-2 add the Coset Polynomial to the CRC-8
byte, thereby creating the “HEC byte”.
Compare the locally computed HEC byte with the
fifth octet of the incoming cell.
If the user configures the Receive Cell Processor to
NOT account for the Coset Polynomial, then the
Receive Cell Processor will go through the following
procedure during HEC byte verification:
Recompute the HEC byte, based upon the values
of bytes 1 through 4 in the received cell.
Compare the locally computed HEC byte with the
fifth octet of the incoming cell.
Writing a “0” to this bit-field configures the Receive Cell
Processor to NOT account for the Coset Polynomial.
Writing a “1” to this bit-field configures the Receive
Cell Processor to account for the Coset Polynomial.
Bit 0—HEC Error Ignore
This “Read/Write” bit-field allows the user to config-
ure the Receive Cell Processor to either discard or
retain cells with HEC errors.
If the user configures the Receive Cell Processor to
discard these errored cells (the default condition),
then all incoming cells containing single-bit (when the
Receive Cell Processor is operating in the “Detection
Mode”) or multi-bit errors in their header, will be dis-
carded and will NOT be written to the Rx FIFO.
Note:
If the Receive Cell Processor is operating in the
“Correction Mode”, then those cells that contain single-bit
errors will be corrected, via the HEC Byte Verification
Algorithm, and will not be discarded).
If the user configures the Receive Cell Processor to
retain these errored cells, then all incoming cells con-
taining single-bit or multi-bit errors in their headers, will
NOT be discarded, and may (depending upon the Idle
or User cell filter settings) be written to the Rx FIFO.
Writing a “0” to this bit-field disables this feature (e.g.,
Receive Cell Processor will discard errored cells).
Writing a “1” to this bit-field enable this feature (e.g.,
Receive Cell Processor will retain errored cells.)
Note:
For more information on this feature, please see
Section 7.3.2.2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT7288IP | CEPT1 Line Interface |
| XRT7288 | CEPT1 Line Interface(CEPT1線接口) |
| XRT7288IW | CEPT1 Line Interface |
| XRT7295AE | E3 (34.368Mbps) Integrated line Receiver |
| XRT7295AE_03 | E3 (34.368Mbps) Integrated line Receiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT7250 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:DS3/E3 FRAMER IC |
| XRT7250ES-PCI | 功能描述:界面開(kāi)發(fā)工具 Evaluation Board for XRT7250 Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V |
| XRT7250IQ100 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:DS3/E3 FRAMER IC |
| XRT7288 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:CEPT1 Line Interface |
| XR-T7288 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:CEPT1 Line Interface |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。